xref: /llvm-project/llvm/test/CodeGen/X86/imul-lea-2.ll (revision 25528d6de70e98683722e28655d8568d5f09b5c7)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
3
4
5define i64 @t1(i64 %a) nounwind readnone {
6; CHECK-LABEL: t1:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    leaq (%rdi,%rdi,8), %rax
9; CHECK-NEXT:    leaq (%rax,%rax,8), %rax
10; CHECK-NEXT:    retq
11entry:
12  %0 = mul i64 %a, 81
13  ret i64 %0
14}
15
16define i64 @t2(i64 %a) nounwind readnone {
17; CHECK-LABEL: t2:
18; CHECK:       # %bb.0: # %entry
19; CHECK-NEXT:    shlq $3, %rdi
20; CHECK-NEXT:    leaq (%rdi,%rdi,4), %rax
21; CHECK-NEXT:    retq
22entry:
23  %0 = mul i64 %a, 40
24  ret i64 %0
25}
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