xref: /llvm-project/llvm/test/CodeGen/X86/horizontal-shuffle-4.ll (revision 69a322fed19b977d15be9500d8653496b73673e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx2 | FileCheck %s
3; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s
4
5;
6; 128-bit Vectors
7;
8
9define <16 x i8> @permute_packss_packss_128(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) {
10; CHECK-LABEL: permute_packss_packss_128:
11; CHECK:       ## %bb.0:
12; CHECK-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
13; CHECK-NEXT:    vpackssdw %xmm3, %xmm2, %xmm1
14; CHECK-NEXT:    vpacksswb %xmm1, %xmm0, %xmm0
15; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,2,3,0]
16; CHECK-NEXT:    ret{{[l|q]}}
17  %1 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1)
18  %2 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a2, <4 x i32> %a3)
19  %3 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %1, <8 x i16> %2)
20  %4 = shufflevector <16 x i8> %3, <16 x i8> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3>
21  ret <16 x i8> %4
22}
23
24define <16 x i8> @permute_packss_packus_128(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) {
25; CHECK-LABEL: permute_packss_packus_128:
26; CHECK:       ## %bb.0:
27; CHECK-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
28; CHECK-NEXT:    vpackusdw %xmm3, %xmm2, %xmm1
29; CHECK-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
30; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,2,3,0]
31; CHECK-NEXT:    ret{{[l|q]}}
32  %1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1)
33  %2 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a2, <4 x i32> %a3)
34  %3 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %1, <8 x i16> %2)
35  %4 = shufflevector <16 x i8> %3, <16 x i8> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3>
36  ret <16 x i8> %4
37}
38
39define <8 x i16> @permute_phadd_phadd_128(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2, <8 x i16> %a3) {
40; CHECK-LABEL: permute_phadd_phadd_128:
41; CHECK:       ## %bb.0:
42; CHECK-NEXT:    vphaddw %xmm1, %xmm0, %xmm0
43; CHECK-NEXT:    vphaddw %xmm3, %xmm2, %xmm1
44; CHECK-NEXT:    vphaddw %xmm1, %xmm0, %xmm0
45; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,2,3,0]
46; CHECK-NEXT:    ret{{[l|q]}}
47  %1 = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1)
48  %2 = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a2, <8 x i16> %a3)
49  %3 = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %1, <8 x i16> %2)
50  %4 = shufflevector <8 x i16> %3, <8 x i16> poison, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
51  ret <8 x i16> %4
52}
53
54;
55; 256-bit Vectors
56;
57
58define <8 x float> @permute_hadd_hadd_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, <8 x float> %a3) {
59; CHECK-LABEL: permute_hadd_hadd_256:
60; CHECK:       ## %bb.0:
61; CHECK-NEXT:    vhaddps %ymm1, %ymm0, %ymm0
62; CHECK-NEXT:    vhaddps %ymm3, %ymm2, %ymm1
63; CHECK-NEXT:    vhaddps %ymm1, %ymm0, %ymm0
64; CHECK-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[1,2,3,0,5,6,7,4]
65; CHECK-NEXT:    ret{{[l|q]}}
66  %1 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1)
67  %2 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a2, <8 x float> %a3)
68  %3 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %1, <8 x float> %2)
69  %4 = shufflevector <8 x float> %3, <8 x float> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7, i32 4>
70  ret <8 x float> %4
71}
72
73define <16 x i16> @permute_phadd_phadd_256(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> %a2, <16 x i16> %a3) {
74; CHECK-LABEL: permute_phadd_phadd_256:
75; CHECK:       ## %bb.0:
76; CHECK-NEXT:    vphaddw %ymm1, %ymm0, %ymm0
77; CHECK-NEXT:    vphaddw %ymm3, %ymm2, %ymm1
78; CHECK-NEXT:    vphaddw %ymm1, %ymm0, %ymm0
79; CHECK-NEXT:    vpshufd {{.*#+}} ymm0 = ymm0[1,2,3,0,5,6,7,4]
80; CHECK-NEXT:    ret{{[l|q]}}
81  %1 = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a0, <16 x i16> %a1)
82  %2 = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a2, <16 x i16> %a3)
83  %3 = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %1, <16 x i16> %2)
84  %4 = shufflevector <16 x i16> %3, <16 x i16> poison, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9>
85  ret <16 x i16> %4
86}
87
88declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>)
89declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
90declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>)
91declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
92
93declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>)
94declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>)
95declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>)
96declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>)
97
98declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>)
99declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>)
100declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>)
101declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>)
102
103declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>)
104declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>)
105declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>)
106declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>)
107
108declare <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16>, <16 x i16>)
109declare <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32>, <8 x i32>)
110declare <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16>, <16 x i16>)
111declare <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32>, <8 x i32>)
112
113declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>)
114declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>)
115declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>)
116declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>)
117