1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=cannonlake | FileCheck %s 3 4; Check the correctness of following test. 5; For this case: 6; In 32-bits targets the <i64 12, ...> will convert to <i32 12, i32 0, ...> in 7; type legalization and turn to <i32 12, i32 undef, ...> in combining due to it 8; only use the low i32 bits. 9; But the fshl is <8 x i64> fshl, the <i32 12, i32 undef, ...> will bitcast to 10; <i64 Element, ...> back. Some like: 11; ============================================================================== 12; // t1: v16i32 = Constant:i32<12>, undef:i32, Constant:i32<12>, undef:i32, ... 13; // t2: v8i64 = bitcast t1 14; // t5: v8i64 = fshl t3, t4, t2 15; ============================================================================== 16; We should make sure not "merging" <i32 12, i32 undef> to <i64 undef> 17; (We can not convert t2 to {i64 undef, i64 undef, ...}) 18; That is not equal with the origin result) 19; 20define void @test_fshl(<8 x i64> %lo, <8 x i64> %hi, ptr %arr) { 21; CHECK-LABEL: test_fshl: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 24; CHECK-NEXT: vpsllq $12, %zmm1, %zmm1 25; CHECK-NEXT: vpsrlq $52, %zmm0, %zmm0 26; CHECK-NEXT: vpternlogq $168, {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0 27; CHECK-NEXT: vmovdqa64 %zmm0, (%eax) 28; CHECK-NEXT: vzeroupper 29; CHECK-NEXT: retl 30entry: 31 %fshl = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %hi, <8 x i64> %lo, <8 x i64> <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>) 32 %res = shufflevector <8 x i64> %fshl, <8 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 6, i32 7> 33 store <8 x i64> %res, ptr %arr, align 64 34 ret void 35} 36 37 38; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn 39declare <8 x i64> @llvm.fshl.v8i64(<8 x i64>, <8 x i64>, <8 x i64>) 40