xref: /llvm-project/llvm/test/CodeGen/X86/fast-isel-int-float-conversion-x86-64.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=SSE2
3; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX
4; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx512f -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX
5
6
7define double @long_to_double_rr(i64 %a) {
8; SSE2-LABEL: long_to_double_rr:
9; SSE2:       # %bb.0: # %entry
10; SSE2-NEXT:    cvtsi2sd %rdi, %xmm0
11; SSE2-NEXT:    retq
12;
13; AVX-LABEL: long_to_double_rr:
14; AVX:       # %bb.0: # %entry
15; AVX-NEXT:    vcvtsi2sd %rdi, %xmm0, %xmm0
16; AVX-NEXT:    retq
17entry:
18  %0 = sitofp i64 %a to double
19  ret double %0
20}
21
22define double @long_to_double_rm(ptr %a) {
23; SSE2-LABEL: long_to_double_rm:
24; SSE2:       # %bb.0: # %entry
25; SSE2-NEXT:    cvtsi2sdq (%rdi), %xmm0
26; SSE2-NEXT:    retq
27;
28; AVX-LABEL: long_to_double_rm:
29; AVX:       # %bb.0: # %entry
30; AVX-NEXT:    vcvtsi2sdq (%rdi), %xmm0, %xmm0
31; AVX-NEXT:    retq
32entry:
33  %0 = load i64, ptr %a
34  %1 = sitofp i64 %0 to double
35  ret double %1
36}
37
38define double @long_to_double_rm_optsize(ptr %a) optsize {
39; SSE2-LABEL: long_to_double_rm_optsize:
40; SSE2:       # %bb.0: # %entry
41; SSE2-NEXT:    cvtsi2sdq (%rdi), %xmm0
42; SSE2-NEXT:    retq
43;
44; AVX-LABEL: long_to_double_rm_optsize:
45; AVX:       # %bb.0: # %entry
46; AVX-NEXT:    vcvtsi2sdq (%rdi), %xmm0, %xmm0
47; AVX-NEXT:    retq
48entry:
49  %0 = load i64, ptr %a
50  %1 = sitofp i64 %0 to double
51  ret double %1
52}
53
54define float @long_to_float_rr(i64 %a) {
55; SSE2-LABEL: long_to_float_rr:
56; SSE2:       # %bb.0: # %entry
57; SSE2-NEXT:    cvtsi2ss %rdi, %xmm0
58; SSE2-NEXT:    retq
59;
60; AVX-LABEL: long_to_float_rr:
61; AVX:       # %bb.0: # %entry
62; AVX-NEXT:    vcvtsi2ss %rdi, %xmm0, %xmm0
63; AVX-NEXT:    retq
64entry:
65  %0 = sitofp i64 %a to float
66  ret float %0
67}
68
69define float @long_to_float_rm(ptr %a) {
70; SSE2-LABEL: long_to_float_rm:
71; SSE2:       # %bb.0: # %entry
72; SSE2-NEXT:    cvtsi2ssq (%rdi), %xmm0
73; SSE2-NEXT:    retq
74;
75; AVX-LABEL: long_to_float_rm:
76; AVX:       # %bb.0: # %entry
77; AVX-NEXT:    vcvtsi2ssq (%rdi), %xmm0, %xmm0
78; AVX-NEXT:    retq
79entry:
80  %0 = load i64, ptr %a
81  %1 = sitofp i64 %0 to float
82  ret float %1
83}
84
85define float @long_to_float_rm_optsize(ptr %a) optsize {
86; SSE2-LABEL: long_to_float_rm_optsize:
87; SSE2:       # %bb.0: # %entry
88; SSE2-NEXT:    cvtsi2ssq (%rdi), %xmm0
89; SSE2-NEXT:    retq
90;
91; AVX-LABEL: long_to_float_rm_optsize:
92; AVX:       # %bb.0: # %entry
93; AVX-NEXT:    vcvtsi2ssq (%rdi), %xmm0, %xmm0
94; AVX-NEXT:    retq
95entry:
96  %0 = load i64, ptr %a
97  %1 = sitofp i64 %0 to float
98  ret float %1
99}
100