xref: /llvm-project/llvm/test/CodeGen/X86/extmul128.ll (revision db25f51e37baf3b804ec541a834d3fd0b6b44118)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
3
4define i128 @i64_sext_i128(i64 %a, i64 %b) {
5; CHECK-LABEL: i64_sext_i128:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    movq %rdi, %rax
8; CHECK-NEXT:    imulq %rsi
9; CHECK-NEXT:    retq
10  %aa = sext i64 %a to i128
11  %bb = sext i64 %b to i128
12  %cc = mul i128 %aa, %bb
13  ret i128 %cc
14}
15define i128 @i64_zext_i128(i64 %a, i64 %b) {
16; CHECK-LABEL: i64_zext_i128:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    movq %rdi, %rax
19; CHECK-NEXT:    mulq %rsi
20; CHECK-NEXT:    retq
21  %aa = zext i64 %a to i128
22  %bb = zext i64 %b to i128
23  %cc = mul i128 %aa, %bb
24  ret i128 %cc
25}
26define i128 @i64_zext_sext_i128(i64 %a, i64 %b) {
27; CHECK-LABEL: i64_zext_sext_i128:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    movq %rdi, %rax
30; CHECK-NEXT:    mulq %rsi
31; CHECK-NEXT:    sarq $63, %rsi
32; CHECK-NEXT:    imulq %rdi, %rsi
33; CHECK-NEXT:    addq %rsi, %rdx
34; CHECK-NEXT:    retq
35  %aa = zext i64 %a to i128
36  %bb = sext i64 %b to i128
37  %cc = mul i128 %aa, %bb
38  ret i128 %cc
39}
40
41define i128 @i64_sext_zext_i128(i64 %a, i64 %b) {
42; CHECK-LABEL: i64_sext_zext_i128:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    movq %rdi, %rax
45; CHECK-NEXT:    movq %rdi, %rcx
46; CHECK-NEXT:    sarq $63, %rcx
47; CHECK-NEXT:    mulq %rsi
48; CHECK-NEXT:    imulq %rsi, %rcx
49; CHECK-NEXT:    addq %rcx, %rdx
50; CHECK-NEXT:    retq
51  %aa = sext i64 %a to i128
52  %bb = zext i64 %b to i128
53  %cc = mul i128 %aa, %bb
54  ret i128 %cc
55}
56