1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O0 -relocation-model=pic -frame-pointer=all < %s | FileCheck %s 3target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" 4target triple = "x86_64-apple-darwin10" 5 6; This file contains functions that may crash llc -O0 7 8; The DIV8 instruction produces results in AH and AL, but we don't want to use 9; AH in 64-bit mode. The hack used must not generate copyFromReg nodes for 10; aliased registers (AX and AL) - RegAllocFast does not like that. 11; PR7312 12define i32 @div8() nounwind { 13; CHECK-LABEL: div8: 14; CHECK: ## %bb.0: ## %entry 15; CHECK-NEXT: pushq %rbp 16; CHECK-NEXT: movq %rsp, %rbp 17; CHECK-NEXT: ## implicit-def: $rax 18; CHECK-NEXT: movb %al, %cl 19; CHECK-NEXT: xorl %eax, %eax 20; CHECK-NEXT: ## kill: def $al killed $al killed $eax 21; CHECK-NEXT: movzbw %al, %ax 22; CHECK-NEXT: divb %cl 23; CHECK-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill 24; CHECK-NEXT: xorl %eax, %eax 25; CHECK-NEXT: ## kill: def $al killed $al killed $eax 26; CHECK-NEXT: movzbw %al, %ax 27; CHECK-NEXT: divb %cl 28; CHECK-NEXT: shrw $8, %ax 29; CHECK-NEXT: ## kill: def $al killed $al killed $ax 30; CHECK-NEXT: cmpb %cl, %al 31; CHECK-NEXT: jae LBB0_2 32; CHECK-NEXT: ## %bb.1: ## %"39" 33; CHECK-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al ## 1-byte Reload 34; CHECK-NEXT: movzbl %al, %eax 35; CHECK-NEXT: ## implicit-def: $ecx 36; CHECK-NEXT: imull %ecx, %eax 37; CHECK-NEXT: ## implicit-def: $ecx 38; CHECK-NEXT: addl %ecx, %eax 39; CHECK-NEXT: ## implicit-def: $ecx 40; CHECK-NEXT: cmpl %ecx, %eax 41; CHECK-NEXT: je LBB0_3 42; CHECK-NEXT: LBB0_2: ## %"40" 43; CHECK-NEXT: ud2 44; CHECK-NEXT: LBB0_3: ## %"41" 45; CHECK-NEXT: ud2 46entry: 47 %0 = trunc i64 undef to i8 ; <i8> [#uses=3] 48 %1 = udiv i8 0, %0 ; <i8> [#uses=1] 49 %2 = urem i8 0, %0 ; <i8> [#uses=1] 50 %3 = icmp uge i8 %2, %0 ; <i1> [#uses=1] 51 br i1 %3, label %"40", label %"39" 52 53"39": ; preds = %"36" 54 %4 = zext i8 %1 to i32 ; <i32> [#uses=1] 55 %5 = mul nsw i32 %4, undef ; <i32> [#uses=1] 56 %6 = add nsw i32 %5, undef ; <i32> [#uses=1] 57 %7 = icmp ne i32 %6, undef ; <i1> [#uses=1] 58 br i1 %7, label %"40", label %"41" 59 60"40": ; preds = %"39", %"36" 61 unreachable 62 63"41": ; preds = %"39" 64 unreachable 65} 66 67; When using fast isel, sdiv is lowered into a sequence of CQO + DIV64. 68; CQO defines implicitly AX and DIV64 uses it implicitly too. 69; When an instruction gets between those two, RegAllocFast was reusing 70; AX for the vreg defined in between and the compiler crashed. 71; 72; An instruction gets between CQO and DIV64 because the load is folded 73; into the division but it requires a sign extension. 74; PR21700 75define i64 @addressModeWith32bitIndex(i32 %V) { 76; CHECK-LABEL: addressModeWith32bitIndex: 77; CHECK: ## %bb.0: 78; CHECK-NEXT: pushq %rbp 79; CHECK-NEXT: .cfi_def_cfa_offset 16 80; CHECK-NEXT: .cfi_offset %rbp, -16 81; CHECK-NEXT: movq %rsp, %rbp 82; CHECK-NEXT: .cfi_def_cfa_register %rbp 83; CHECK-NEXT: xorl %eax, %eax 84; CHECK-NEXT: movl %eax, %ecx 85; CHECK-NEXT: movq %rcx, %rax 86; CHECK-NEXT: cqto 87; CHECK-NEXT: movslq %edi, %rsi 88; CHECK-NEXT: idivq (%rcx,%rsi,8) 89; CHECK-NEXT: popq %rbp 90; CHECK-NEXT: retq 91 %gep = getelementptr i64, ptr null, i32 %V 92 %load = load i64, ptr %gep 93 %sdiv = sdiv i64 0, %load 94 ret i64 %sdiv 95} 96