xref: /llvm-project/llvm/test/CodeGen/X86/consecutive-load-shuffle.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-pc-windows | FileCheck %s
3
4; We should be able to prodcue a single 128-bit load for these two 64-bit loads.
5; But we previously weren't because we weren't consistently looking through
6; WrapperRIP.
7
8@f = local_unnamed_addr global [4 x float] zeroinitializer, align 16
9@ms = common local_unnamed_addr global <4 x float> zeroinitializer, align 16
10
11define void @foo2() {
12; CHECK-LABEL: foo2:
13; CHECK:       # %bb.0: # %entry
14; CHECK-NEXT:    movaps f(%rip), %xmm0
15; CHECK-NEXT:    movaps %xmm0, ms(%rip)
16; CHECK-NEXT:    retq
17entry:
18  %0 = load <2 x float>, ptr getelementptr inbounds ([4 x float], ptr @f, i64 0, i64 2), align 8
19  %shuffle.i10 = shufflevector <2 x float> %0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
20  %1 = load <2 x float>, ptr @f, align 16
21  %shuffle.i7 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
22  %shuffle.i = shufflevector <4 x float> %shuffle.i7, <4 x float> %shuffle.i10, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
23  store <4 x float> %shuffle.i, ptr @ms, align 16
24  ret void
25}
26