xref: /llvm-project/llvm/test/CodeGen/X86/combine-sub-ssat.ll (revision 8f82d8ee760360a68de47d75d6a1851dacbdb8ef) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX
8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX
9
10declare  i32 @llvm.ssub.sat.i32  (i32, i32)
11declare  i64 @llvm.ssub.sat.i64  (i64, i64)
12declare  <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
13
14; fold (ssub_sat x, undef) -> 0
15define i32 @combine_undef_i32(i32 %a0) {
16; CHECK-LABEL: combine_undef_i32:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    xorl %eax, %eax
19; CHECK-NEXT:    retq
20  %res = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 undef)
21  ret i32 %res
22}
23
24define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {
25; SSE-LABEL: combine_undef_v8i16:
26; SSE:       # %bb.0:
27; SSE-NEXT:    xorps %xmm0, %xmm0
28; SSE-NEXT:    retq
29;
30; AVX-LABEL: combine_undef_v8i16:
31; AVX:       # %bb.0:
32; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
33; AVX-NEXT:    retq
34  %res = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)
35  ret <8 x i16> %res
36}
37
38; fold (ssub_sat c1, c2) -> c3
39define i32 @combine_constfold_i32() {
40; CHECK-LABEL: combine_constfold_i32:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    movl $-2147483547, %eax # imm = 0x80000065
43; CHECK-NEXT:    retq
44  %res = call i32 @llvm.ssub.sat.i32(i32 100, i32 2147483647)
45  ret i32 %res
46}
47
48define <8 x i16> @combine_constfold_v8i16() {
49; SSE-LABEL: combine_constfold_v8i16:
50; SSE:       # %bb.0:
51; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,2,254,0,65534,65282,32786,2]
52; SSE-NEXT:    retq
53;
54; AVX-LABEL: combine_constfold_v8i16:
55; AVX:       # %bb.0:
56; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65535,2,254,0,65534,65282,32786,2]
57; AVX-NEXT:    retq
58  %res = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> <i16 0, i16 1, i16 255, i16 65535, i16 -1, i16 -255, i16 -32760, i16 1>, <8 x i16> <i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 -10, i16 65535>)
59  ret <8 x i16> %res
60}
61
62define <8 x i16> @combine_constfold_undef_v8i16() {
63; SSE-LABEL: combine_constfold_undef_v8i16:
64; SSE:       # %bb.0:
65; SSE-NEXT:    movaps {{.*#+}} xmm0 = [0,0,0,0,65534,65282,32786,2]
66; SSE-NEXT:    retq
67;
68; AVX-LABEL: combine_constfold_undef_v8i16:
69; AVX:       # %bb.0:
70; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [0,0,0,0,65534,65282,32786,2]
71; AVX-NEXT:    retq
72  %res = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> <i16 undef, i16 1, i16 undef, i16 65535, i16 -1, i16 -255, i16 -32760, i16 1>, <8 x i16> <i16 1, i16 undef, i16 undef, i16 65535, i16 1, i16 65535, i16 -10, i16 65535>)
73  ret <8 x i16> %res
74}
75
76; fold (ssub_sat x, 0) -> x
77define i32 @combine_zero_i32(i32 %a0) {
78; CHECK-LABEL: combine_zero_i32:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    movl %edi, %eax
81; CHECK-NEXT:    retq
82  %1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 0)
83  ret i32 %1
84}
85
86define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) {
87; CHECK-LABEL: combine_zero_v8i16:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    retq
90  %1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer)
91  ret <8 x i16> %1
92}
93
94; fold (ssub_sat x, x) -> 0
95define i32 @combine_self_i32(i32 %a0) {
96; CHECK-LABEL: combine_self_i32:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    xorl %eax, %eax
99; CHECK-NEXT:    retq
100  %1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 %a0)
101  ret i32 %1
102}
103
104define <8 x i16> @combine_self_v8i16(<8 x i16> %a0) {
105; SSE-LABEL: combine_self_v8i16:
106; SSE:       # %bb.0:
107; SSE-NEXT:    xorps %xmm0, %xmm0
108; SSE-NEXT:    retq
109;
110; AVX-LABEL: combine_self_v8i16:
111; AVX:       # %bb.0:
112; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
113; AVX-NEXT:    retq
114  %1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> %a0)
115  ret <8 x i16> %1
116}
117
118; fold (ssub_sat x, y) -> (sub x, y) iff no overflow
119define i32 @combine_no_overflow_i32(i32 %a0, i32 %a1) {
120; CHECK-LABEL: combine_no_overflow_i32:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    movl %edi, %eax
123; CHECK-NEXT:    sarl $16, %eax
124; CHECK-NEXT:    shrl $16, %esi
125; CHECK-NEXT:    subl %esi, %eax
126; CHECK-NEXT:    retq
127  %1 = ashr i32 %a0, 16
128  %2 = lshr i32 %a1, 16
129  %3 = call i32 @llvm.ssub.sat.i32(i32 %1, i32 %2)
130  ret i32 %3
131}
132
133define <8 x i16> @combine_no_overflow_v8i16(<8 x i16> %a0, <8 x i16> %a1) {
134; SSE-LABEL: combine_no_overflow_v8i16:
135; SSE:       # %bb.0:
136; SSE-NEXT:    psraw $10, %xmm0
137; SSE-NEXT:    psrlw $10, %xmm1
138; SSE-NEXT:    psubw %xmm1, %xmm0
139; SSE-NEXT:    retq
140;
141; AVX-LABEL: combine_no_overflow_v8i16:
142; AVX:       # %bb.0:
143; AVX-NEXT:    vpsraw $10, %xmm0, %xmm0
144; AVX-NEXT:    vpsrlw $10, %xmm1, %xmm1
145; AVX-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
146; AVX-NEXT:    retq
147  %1 = ashr <8 x i16> %a0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
148  %2 = lshr <8 x i16> %a1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
149  %3 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %1, <8 x i16> %2)
150  ret <8 x i16> %3
151}
152
153; fold (ssub_sat (shuffle x, u, m), (shuffle y, u, m)) -> (shuffle (ssub_sat x, y), u, m)
154define <8 x i16> @combine_shuffle_shuffle_v8i16(<8 x i16> %x0, <8 x i16> %y0) {
155; SSE-LABEL: combine_shuffle_shuffle_v8i16:
156; SSE:       # %bb.0:
157; SSE-NEXT:    psubsw %xmm1, %xmm0
158; SSE-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
159; SSE-NEXT:    retq
160;
161; AVX-LABEL: combine_shuffle_shuffle_v8i16:
162; AVX:       # %bb.0:
163; AVX-NEXT:    vpsubsw %xmm1, %xmm0, %xmm0
164; AVX-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
165; AVX-NEXT:    retq
166  %x1= shufflevector <8 x i16> %x0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
167  %y1 = shufflevector <8 x i16> %y0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
168  %res = tail call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x1, <8 x i16> %y1)
169  ret <8 x i16> %res
170}
171