1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,VTEST,VTEST-AVX1 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,VTEST,VTEST-AVX2 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=CHECK,MOVMSK,MOVMSK-AVX1 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=CHECK,MOVMSK,MOVMSK-AVX2 6 7declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) 8declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) 9 10; Use widest possible vector for movmsk comparisons (PR37087) 11 12define i1 @movmskps_noneof_bitcast_v4f64(<4 x double> %a0) { 13; VTEST-LABEL: movmskps_noneof_bitcast_v4f64: 14; VTEST: # %bb.0: 15; VTEST-NEXT: vxorpd %xmm1, %xmm1, %xmm1 16; VTEST-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 17; VTEST-NEXT: vtestpd %ymm0, %ymm0 18; VTEST-NEXT: sete %al 19; VTEST-NEXT: vzeroupper 20; VTEST-NEXT: retq 21; 22; MOVMSK-LABEL: movmskps_noneof_bitcast_v4f64: 23; MOVMSK: # %bb.0: 24; MOVMSK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 25; MOVMSK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 26; MOVMSK-NEXT: vmovmskpd %ymm0, %eax 27; MOVMSK-NEXT: testl %eax, %eax 28; MOVMSK-NEXT: sete %al 29; MOVMSK-NEXT: vzeroupper 30; MOVMSK-NEXT: retq 31 %1 = fcmp oeq <4 x double> %a0, zeroinitializer 32 %2 = sext <4 x i1> %1 to <4 x i64> 33 %3 = bitcast <4 x i64> %2 to <8 x float> 34 %4 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %3) 35 %5 = icmp eq i32 %4, 0 36 ret i1 %5 37} 38 39define i1 @movmskps_allof_bitcast_v4f64(<4 x double> %a0) { 40; VTEST-AVX1-LABEL: movmskps_allof_bitcast_v4f64: 41; VTEST-AVX1: # %bb.0: 42; VTEST-AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1 43; VTEST-AVX1-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 44; VTEST-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 45; VTEST-AVX1-NEXT: vtestpd %ymm1, %ymm0 46; VTEST-AVX1-NEXT: setb %al 47; VTEST-AVX1-NEXT: vzeroupper 48; VTEST-AVX1-NEXT: retq 49; 50; VTEST-AVX2-LABEL: movmskps_allof_bitcast_v4f64: 51; VTEST-AVX2: # %bb.0: 52; VTEST-AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 53; VTEST-AVX2-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 54; VTEST-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 55; VTEST-AVX2-NEXT: vtestpd %ymm1, %ymm0 56; VTEST-AVX2-NEXT: setb %al 57; VTEST-AVX2-NEXT: vzeroupper 58; VTEST-AVX2-NEXT: retq 59; 60; MOVMSK-LABEL: movmskps_allof_bitcast_v4f64: 61; MOVMSK: # %bb.0: 62; MOVMSK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 63; MOVMSK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 64; MOVMSK-NEXT: vmovmskpd %ymm0, %eax 65; MOVMSK-NEXT: cmpl $15, %eax 66; MOVMSK-NEXT: sete %al 67; MOVMSK-NEXT: vzeroupper 68; MOVMSK-NEXT: retq 69 %1 = fcmp oeq <4 x double> %a0, zeroinitializer 70 %2 = sext <4 x i1> %1 to <4 x i64> 71 %3 = bitcast <4 x i64> %2 to <8 x float> 72 %4 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %3) 73 %5 = icmp eq i32 %4, 255 74 ret i1 %5 75} 76 77; 78; TODO - Avoid sign extension ops when just extracting the sign bits. 79; 80 81define i32 @movmskpd_cmpgt_v4i64(<4 x i64> %a0) { 82; VTEST-AVX1-LABEL: movmskpd_cmpgt_v4i64: 83; VTEST-AVX1: # %bb.0: 84; VTEST-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 85; VTEST-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1 86; VTEST-AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] 87; VTEST-AVX1-NEXT: vmovmskpd %ymm0, %eax 88; VTEST-AVX1-NEXT: vzeroupper 89; VTEST-AVX1-NEXT: retq 90; 91; VTEST-AVX2-LABEL: movmskpd_cmpgt_v4i64: 92; VTEST-AVX2: # %bb.0: 93; VTEST-AVX2-NEXT: vmovmskpd %ymm0, %eax 94; VTEST-AVX2-NEXT: vzeroupper 95; VTEST-AVX2-NEXT: retq 96; 97; MOVMSK-AVX1-LABEL: movmskpd_cmpgt_v4i64: 98; MOVMSK-AVX1: # %bb.0: 99; MOVMSK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 100; MOVMSK-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1 101; MOVMSK-AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] 102; MOVMSK-AVX1-NEXT: vmovmskpd %ymm0, %eax 103; MOVMSK-AVX1-NEXT: vzeroupper 104; MOVMSK-AVX1-NEXT: retq 105; 106; MOVMSK-AVX2-LABEL: movmskpd_cmpgt_v4i64: 107; MOVMSK-AVX2: # %bb.0: 108; MOVMSK-AVX2-NEXT: vmovmskpd %ymm0, %eax 109; MOVMSK-AVX2-NEXT: vzeroupper 110; MOVMSK-AVX2-NEXT: retq 111 %1 = icmp sgt <4 x i64> zeroinitializer, %a0 112 %2 = sext <4 x i1> %1 to <4 x i64> 113 %3 = bitcast <4 x i64> %2 to <4 x double> 114 %4 = tail call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %3) 115 ret i32 %4 116} 117 118define i32 @movmskps_ashr_v8i32(<8 x i32> %a0) { 119; VTEST-AVX1-LABEL: movmskps_ashr_v8i32: 120; VTEST-AVX1: # %bb.0: 121; VTEST-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 122; VTEST-AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] 123; VTEST-AVX1-NEXT: vmovmskps %ymm0, %eax 124; VTEST-AVX1-NEXT: vzeroupper 125; VTEST-AVX1-NEXT: retq 126; 127; VTEST-AVX2-LABEL: movmskps_ashr_v8i32: 128; VTEST-AVX2: # %bb.0: 129; VTEST-AVX2-NEXT: vmovmskps %ymm0, %eax 130; VTEST-AVX2-NEXT: vzeroupper 131; VTEST-AVX2-NEXT: retq 132; 133; MOVMSK-AVX1-LABEL: movmskps_ashr_v8i32: 134; MOVMSK-AVX1: # %bb.0: 135; MOVMSK-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 136; MOVMSK-AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] 137; MOVMSK-AVX1-NEXT: vmovmskps %ymm0, %eax 138; MOVMSK-AVX1-NEXT: vzeroupper 139; MOVMSK-AVX1-NEXT: retq 140; 141; MOVMSK-AVX2-LABEL: movmskps_ashr_v8i32: 142; MOVMSK-AVX2: # %bb.0: 143; MOVMSK-AVX2-NEXT: vmovmskps %ymm0, %eax 144; MOVMSK-AVX2-NEXT: vzeroupper 145; MOVMSK-AVX2-NEXT: retq 146 %1 = ashr <8 x i32> %a0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31> 147 %2 = bitcast <8 x i32> %1 to <8 x float> 148 %3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2) 149 ret i32 %3 150} 151 152define i32 @movmskps_sext_v4i64(<4 x i32> %a0) { 153; VTEST-AVX1-LABEL: movmskps_sext_v4i64: 154; VTEST-AVX1: # %bb.0: 155; VTEST-AVX1-NEXT: vpmovsxdq %xmm0, %xmm1 156; VTEST-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] 157; VTEST-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 158; VTEST-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 159; VTEST-AVX1-NEXT: vmovmskpd %ymm0, %eax 160; VTEST-AVX1-NEXT: vzeroupper 161; VTEST-AVX1-NEXT: retq 162; 163; VTEST-AVX2-LABEL: movmskps_sext_v4i64: 164; VTEST-AVX2: # %bb.0: 165; VTEST-AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 166; VTEST-AVX2-NEXT: vmovmskpd %ymm0, %eax 167; VTEST-AVX2-NEXT: vzeroupper 168; VTEST-AVX2-NEXT: retq 169; 170; MOVMSK-AVX1-LABEL: movmskps_sext_v4i64: 171; MOVMSK-AVX1: # %bb.0: 172; MOVMSK-AVX1-NEXT: vpmovsxdq %xmm0, %xmm1 173; MOVMSK-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] 174; MOVMSK-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 175; MOVMSK-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 176; MOVMSK-AVX1-NEXT: vmovmskpd %ymm0, %eax 177; MOVMSK-AVX1-NEXT: vzeroupper 178; MOVMSK-AVX1-NEXT: retq 179; 180; MOVMSK-AVX2-LABEL: movmskps_sext_v4i64: 181; MOVMSK-AVX2: # %bb.0: 182; MOVMSK-AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 183; MOVMSK-AVX2-NEXT: vmovmskpd %ymm0, %eax 184; MOVMSK-AVX2-NEXT: vzeroupper 185; MOVMSK-AVX2-NEXT: retq 186 %1 = sext <4 x i32> %a0 to <4 x i64> 187 %2 = bitcast <4 x i64> %1 to <4 x double> 188 %3 = tail call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %2) 189 ret i32 %3 190} 191 192define i32 @movmskps_sext_v8i32(<8 x i16> %a0) { 193; VTEST-AVX1-LABEL: movmskps_sext_v8i32: 194; VTEST-AVX1: # %bb.0: 195; VTEST-AVX1-NEXT: vpmovsxwd %xmm0, %xmm1 196; VTEST-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] 197; VTEST-AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 198; VTEST-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 199; VTEST-AVX1-NEXT: vmovmskps %ymm0, %eax 200; VTEST-AVX1-NEXT: vzeroupper 201; VTEST-AVX1-NEXT: retq 202; 203; VTEST-AVX2-LABEL: movmskps_sext_v8i32: 204; VTEST-AVX2: # %bb.0: 205; VTEST-AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 206; VTEST-AVX2-NEXT: vmovmskps %ymm0, %eax 207; VTEST-AVX2-NEXT: vzeroupper 208; VTEST-AVX2-NEXT: retq 209; 210; MOVMSK-AVX1-LABEL: movmskps_sext_v8i32: 211; MOVMSK-AVX1: # %bb.0: 212; MOVMSK-AVX1-NEXT: vpmovsxwd %xmm0, %xmm1 213; MOVMSK-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] 214; MOVMSK-AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 215; MOVMSK-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 216; MOVMSK-AVX1-NEXT: vmovmskps %ymm0, %eax 217; MOVMSK-AVX1-NEXT: vzeroupper 218; MOVMSK-AVX1-NEXT: retq 219; 220; MOVMSK-AVX2-LABEL: movmskps_sext_v8i32: 221; MOVMSK-AVX2: # %bb.0: 222; MOVMSK-AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 223; MOVMSK-AVX2-NEXT: vmovmskps %ymm0, %eax 224; MOVMSK-AVX2-NEXT: vzeroupper 225; MOVMSK-AVX2-NEXT: retq 226 %1 = sext <8 x i16> %a0 to <8 x i32> 227 %2 = bitcast <8 x i32> %1 to <8 x float> 228 %3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2) 229 ret i32 %3 230} 231 232define i32 @movmskps_concat_v4f32(<4 x float> %a0, <4 x float> %a1) { 233; VTEST-LABEL: movmskps_concat_v4f32: 234; VTEST: # %bb.0: 235; VTEST-NEXT: vorps %xmm1, %xmm0, %xmm0 236; VTEST-NEXT: xorl %eax, %eax 237; VTEST-NEXT: vtestps %xmm0, %xmm0 238; VTEST-NEXT: setne %al 239; VTEST-NEXT: negl %eax 240; VTEST-NEXT: retq 241; 242; MOVMSK-LABEL: movmskps_concat_v4f32: 243; MOVMSK: # %bb.0: 244; MOVMSK-NEXT: vorps %xmm1, %xmm0, %xmm0 245; MOVMSK-NEXT: vmovmskps %xmm0, %ecx 246; MOVMSK-NEXT: xorl %eax, %eax 247; MOVMSK-NEXT: negl %ecx 248; MOVMSK-NEXT: sbbl %eax, %eax 249; MOVMSK-NEXT: retq 250 %1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 251 %2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1) 252 %3 = icmp ne i32 %2, 0 253 %4 = sext i1 %3 to i32 254 ret i32 %4 255} 256 257define i32 @movmskps_demanded_concat_v4f32(<4 x float> %a0, <4 x float> %a1) { 258; CHECK-LABEL: movmskps_demanded_concat_v4f32: 259; CHECK: # %bb.0: 260; CHECK-NEXT: vmovmskps %xmm0, %ecx 261; CHECK-NEXT: andl $3, %ecx 262; CHECK-NEXT: xorl %eax, %eax 263; CHECK-NEXT: negl %ecx 264; CHECK-NEXT: sbbl %eax, %eax 265; CHECK-NEXT: retq 266 %1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 267 %2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1) 268 %3 = and i32 %2, 3 269 %4 = icmp ne i32 %3, 0 270 %5 = sext i1 %4 to i32 271 ret i32 %5 272} 273