1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 2# RUN: llc -mtriple=x86_64-pc-linux-gnu -verify-coalescing -run-pass=register-coalescer -o - %s | FileCheck %s 3 4# The %1 = MOV32r0 is rematerialized as a subregister of %2. The 5# implicit-def %1 operand needs to have an undef added, just like the 6# main result operand. 7 8--- 9name: remat_into_subregister_set_undef_implicit_operand_subregisters 10tracksRegLiveness: true 11body: | 12 ; CHECK-LABEL: name: remat_into_subregister_set_undef_implicit_operand_subregisters 13 ; CHECK: bb.0: 14 ; CHECK-NEXT: successors: %bb.1(0x80000000) 15 ; CHECK-NEXT: liveins: $rdi 16 ; CHECK-NEXT: {{ $}} 17 ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]] 18 ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_1]] 19 ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_32bit, implicit-def [[MOV32r0_2]] 20 ; CHECK-NEXT: {{ $}} 21 ; CHECK-NEXT: bb.1: 22 ; CHECK-NEXT: successors: %bb.2(0x80000000) 23 ; CHECK-NEXT: {{ $}} 24 ; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = XOR32ri [[MOV32r0_2]].sub_32bit, 1, implicit-def dead $eflags 25 ; CHECK-NEXT: {{ $}} 26 ; CHECK-NEXT: bb.2: 27 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) 28 ; CHECK-NEXT: {{ $}} 29 ; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed undef $eflags 30 ; CHECK-NEXT: {{ $}} 31 ; CHECK-NEXT: bb.3: 32 ; CHECK-NEXT: successors: %bb.4(0x80000000) 33 ; CHECK-NEXT: {{ $}} 34 ; CHECK-NEXT: bb.4: 35 ; CHECK-NEXT: successors: %bb.1(0x80000000) 36 ; CHECK-NEXT: {{ $}} 37 ; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[MOV32r0_1]] 38 ; CHECK-NEXT: dead [[SHL64ri:%[0-9]+]]:gr64_nosp = SHL64ri [[MOV32r0_]], 4, implicit-def dead $eflags 39 ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = COPY [[MOV32r0_2]].sub_32bit 40 ; CHECK-NEXT: JMP_1 %bb.1 41 bb.0: 42 liveins: $rdi 43 44 undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0 45 %1:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def %1 46 undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %2 47 48 bb.1: 49 %2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags 50 51 bb.2: 52 JCC_1 %bb.4, 5, implicit killed undef $eflags 53 54 bb.3: 55 56 bb.4: 57 dead %3:gr32 = MOV32rr %1 58 dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags 59 %1:gr32 = COPY %2.sub_32bit 60 JMP_1 %bb.1 61 62... 63 64# Same, except the implicit-def on the original instruction already 65# has a subregister index. 66 67--- 68name: remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg 69tracksRegLiveness: true 70body: | 71 ; CHECK-LABEL: name: remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg 72 ; CHECK: bb.0: 73 ; CHECK-NEXT: successors: %bb.1(0x80000000) 74 ; CHECK-NEXT: liveins: $rdi 75 ; CHECK-NEXT: {{ $}} 76 ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]] 77 ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_1]].sub_8bit 78 ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_8bit, implicit-def [[MOV32r0_2]] 79 ; CHECK-NEXT: {{ $}} 80 ; CHECK-NEXT: bb.1: 81 ; CHECK-NEXT: successors: %bb.2(0x80000000) 82 ; CHECK-NEXT: {{ $}} 83 ; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = XOR32ri [[MOV32r0_2]].sub_32bit, 1, implicit-def dead $eflags 84 ; CHECK-NEXT: {{ $}} 85 ; CHECK-NEXT: bb.2: 86 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) 87 ; CHECK-NEXT: {{ $}} 88 ; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed undef $eflags 89 ; CHECK-NEXT: {{ $}} 90 ; CHECK-NEXT: bb.3: 91 ; CHECK-NEXT: successors: %bb.4(0x80000000) 92 ; CHECK-NEXT: {{ $}} 93 ; CHECK-NEXT: bb.4: 94 ; CHECK-NEXT: successors: %bb.1(0x80000000) 95 ; CHECK-NEXT: {{ $}} 96 ; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[MOV32r0_1]] 97 ; CHECK-NEXT: dead [[SHL64ri:%[0-9]+]]:gr64_nosp = SHL64ri [[MOV32r0_]], 4, implicit-def dead $eflags 98 ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = COPY [[MOV32r0_2]].sub_32bit 99 ; CHECK-NEXT: JMP_1 %bb.1 100 bb.0: 101 liveins: $rdi 102 103 undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0 104 %1:gr32 = MOV32r0 implicit-def dead $eflags, undef implicit-def %1.sub_8bit 105 undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %2 106 107 bb.1: 108 %2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags 109 110 bb.2: 111 JCC_1 %bb.4, 5, implicit killed undef $eflags 112 113 bb.3: 114 115 bb.4: 116 dead %3:gr32 = MOV32rr %1 117 dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags 118 %1:gr32 = COPY %2.sub_32bit 119 JMP_1 %bb.1 120 121... 122