1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -verify-coalescing -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -verify-coalescing -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -verify-coalescing -mattr=+avx | FileCheck %s --check-prefix=AVX 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -verify-coalescing -mattr=+avx512f | FileCheck %s --check-prefix=AVX512 6 7; PR30607 8 9define <2 x double> @insert_f64(double %a0, <2 x double> %a1) { 10; SSE2-LABEL: insert_f64: 11; SSE2: # %bb.0: 12; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] 13; SSE2-NEXT: retq 14; 15; SSE41-LABEL: insert_f64: 16; SSE41: # %bb.0: 17; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] 18; SSE41-NEXT: retq 19; 20; AVX-LABEL: insert_f64: 21; AVX: # %bb.0: 22; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] 23; AVX-NEXT: retq 24; 25; AVX512-LABEL: insert_f64: 26; AVX512: # %bb.0: 27; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] 28; AVX512-NEXT: retq 29 %1 = insertelement <2 x double> %a1, double %a0, i32 0 30 ret <2 x double> %1 31} 32 33define <4 x float> @insert_f32(float %a0, <4 x float> %a1) { 34; SSE2-LABEL: insert_f32: 35; SSE2: # %bb.0: 36; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] 37; SSE2-NEXT: movaps %xmm1, %xmm0 38; SSE2-NEXT: retq 39; 40; SSE41-LABEL: insert_f32: 41; SSE41: # %bb.0: 42; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] 43; SSE41-NEXT: retq 44; 45; AVX-LABEL: insert_f32: 46; AVX: # %bb.0: 47; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] 48; AVX-NEXT: retq 49; 50; AVX512-LABEL: insert_f32: 51; AVX512: # %bb.0: 52; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] 53; AVX512-NEXT: retq 54 %1 = insertelement <4 x float> %a1, float %a0, i32 0 55 ret <4 x float> %1 56} 57