1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefix=X86 3; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefix=X64 4; RUN: llc < %s -mtriple=i686-unknown- -mcpu=i486 | FileCheck %s --check-prefix=I486 5; RUN: llc < %s -mtriple=i686-unknown- -mcpu=znver1 | FileCheck %s --check-prefix=X86 6; RUN: llc < %s -mtriple=i686-unknown- -mcpu=lakemont | FileCheck %s --check-prefix=X86 7 8; Basic 64-bit cmpxchg 9define void @t1(ptr nocapture %p) nounwind ssp { 10; X86-LABEL: t1: 11; X86: # %bb.0: # %entry 12; X86-NEXT: pushl %ebx 13; X86-NEXT: pushl %esi 14; X86-NEXT: movl {{[0-9]+}}(%esp), %esi 15; X86-NEXT: xorl %eax, %eax 16; X86-NEXT: xorl %edx, %edx 17; X86-NEXT: xorl %ecx, %ecx 18; X86-NEXT: movl $1, %ebx 19; X86-NEXT: lock cmpxchg8b (%esi) 20; X86-NEXT: popl %esi 21; X86-NEXT: popl %ebx 22; X86-NEXT: retl 23; 24; X64-LABEL: t1: 25; X64: # %bb.0: # %entry 26; X64-NEXT: movl $1, %ecx 27; X64-NEXT: xorl %eax, %eax 28; X64-NEXT: lock cmpxchgq %rcx, (%rdi) 29; X64-NEXT: retq 30; 31; I486-LABEL: t1: 32; I486: # %bb.0: # %entry 33; I486-NEXT: pushl %ebp 34; I486-NEXT: movl %esp, %ebp 35; I486-NEXT: andl $-8, %esp 36; I486-NEXT: subl $8, %esp 37; I486-NEXT: movl 8(%ebp), %eax 38; I486-NEXT: movl $0, {{[0-9]+}}(%esp) 39; I486-NEXT: movl $0, (%esp) 40; I486-NEXT: movl %esp, %ecx 41; I486-NEXT: pushl $5 42; I486-NEXT: pushl $5 43; I486-NEXT: pushl $0 44; I486-NEXT: pushl $1 45; I486-NEXT: pushl %ecx 46; I486-NEXT: pushl %eax 47; I486-NEXT: calll __atomic_compare_exchange_8@PLT 48; I486-NEXT: addl $24, %esp 49; I486-NEXT: movl %ebp, %esp 50; I486-NEXT: popl %ebp 51; I486-NEXT: retl 52entry: 53 %r = cmpxchg ptr %p, i64 0, i64 1 seq_cst seq_cst 54 ret void 55} 56 57