1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=X64 3; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+bmi,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR 4 5; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/bmi-builtins.c 6 7; 8; AMD Intrinsics 9; 10 11define i64 @test__andn_u64(i64 %a0, i64 %a1) { 12; X64-LABEL: test__andn_u64: 13; X64: # %bb.0: 14; X64-NEXT: movq %rdi, %rax 15; X64-NEXT: xorq $-1, %rax 16; X64-NEXT: andq %rsi, %rax 17; X64-NEXT: retq 18; 19; EGPR-LABEL: test__andn_u64: 20; EGPR: # %bb.0: 21; EGPR-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8] 22; EGPR-NEXT: xorq $-1, %rax # encoding: [0x48,0x83,0xf0,0xff] 23; EGPR-NEXT: andq %rsi, %rax # encoding: [0x48,0x21,0xf0] 24; EGPR-NEXT: retq # encoding: [0xc3] 25 %xor = xor i64 %a0, -1 26 %res = and i64 %xor, %a1 27 ret i64 %res 28} 29 30define i64 @test__bextr_u64(i64 %a0, i64 %a1) { 31; X64-LABEL: test__bextr_u64: 32; X64: # %bb.0: 33; X64-NEXT: bextrq %rsi, %rdi, %rax 34; X64-NEXT: retq 35; 36; EGPR-LABEL: test__bextr_u64: 37; EGPR: # %bb.0: 38; EGPR-NEXT: bextrq %rsi, %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc8,0xf7,0xc7] 39; EGPR-NEXT: retq # encoding: [0xc3] 40 %res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %a1) 41 ret i64 %res 42} 43 44define i64 @test__blsi_u64(i64 %a0) { 45; X64-LABEL: test__blsi_u64: 46; X64: # %bb.0: 47; X64-NEXT: xorl %eax, %eax 48; X64-NEXT: subq %rdi, %rax 49; X64-NEXT: andq %rdi, %rax 50; X64-NEXT: retq 51; 52; EGPR-LABEL: test__blsi_u64: 53; EGPR: # %bb.0: 54; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] 55; EGPR-NEXT: subq %rdi, %rax # encoding: [0x48,0x29,0xf8] 56; EGPR-NEXT: andq %rdi, %rax # encoding: [0x48,0x21,0xf8] 57; EGPR-NEXT: retq # encoding: [0xc3] 58 %neg = sub i64 0, %a0 59 %res = and i64 %a0, %neg 60 ret i64 %res 61} 62 63define i64 @test__blsmsk_u64(i64 %a0) { 64; X64-LABEL: test__blsmsk_u64: 65; X64: # %bb.0: 66; X64-NEXT: leaq -1(%rdi), %rax 67; X64-NEXT: xorq %rdi, %rax 68; X64-NEXT: retq 69; 70; EGPR-LABEL: test__blsmsk_u64: 71; EGPR: # %bb.0: 72; EGPR-NEXT: leaq -1(%rdi), %rax # encoding: [0x48,0x8d,0x47,0xff] 73; EGPR-NEXT: xorq %rdi, %rax # encoding: [0x48,0x31,0xf8] 74; EGPR-NEXT: retq # encoding: [0xc3] 75 %dec = sub i64 %a0, 1 76 %res = xor i64 %a0, %dec 77 ret i64 %res 78} 79 80define i64 @test__blsr_u64(i64 %a0) { 81; X64-LABEL: test__blsr_u64: 82; X64: # %bb.0: 83; X64-NEXT: leaq -1(%rdi), %rax 84; X64-NEXT: andq %rdi, %rax 85; X64-NEXT: retq 86; 87; EGPR-LABEL: test__blsr_u64: 88; EGPR: # %bb.0: 89; EGPR-NEXT: leaq -1(%rdi), %rax # encoding: [0x48,0x8d,0x47,0xff] 90; EGPR-NEXT: andq %rdi, %rax # encoding: [0x48,0x21,0xf8] 91; EGPR-NEXT: retq # encoding: [0xc3] 92 %dec = sub i64 %a0, 1 93 %res = and i64 %a0, %dec 94 ret i64 %res 95} 96 97define i64 @test__tzcnt_u64(i64 %a0) { 98; X64-LABEL: test__tzcnt_u64: 99; X64: # %bb.0: 100; X64-NEXT: tzcntq %rdi, %rax 101; X64-NEXT: retq 102; 103; EGPR-LABEL: test__tzcnt_u64: 104; EGPR: # %bb.0: 105; EGPR-NEXT: tzcntq %rdi, %rax # encoding: [0xf3,0x48,0x0f,0xbc,0xc7] 106; EGPR-NEXT: retq # encoding: [0xc3] 107 %cmp = icmp ne i64 %a0, 0 108 %cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 false) 109 ret i64 %cttz 110} 111 112; 113; Intel intrinsics 114; 115 116define i64 @test_andn_u64(i64 %a0, i64 %a1) { 117; X64-LABEL: test_andn_u64: 118; X64: # %bb.0: 119; X64-NEXT: movq %rdi, %rax 120; X64-NEXT: xorq $-1, %rax 121; X64-NEXT: andq %rsi, %rax 122; X64-NEXT: retq 123; 124; EGPR-LABEL: test_andn_u64: 125; EGPR: # %bb.0: 126; EGPR-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8] 127; EGPR-NEXT: xorq $-1, %rax # encoding: [0x48,0x83,0xf0,0xff] 128; EGPR-NEXT: andq %rsi, %rax # encoding: [0x48,0x21,0xf0] 129; EGPR-NEXT: retq # encoding: [0xc3] 130 %xor = xor i64 %a0, -1 131 %res = and i64 %xor, %a1 132 ret i64 %res 133} 134 135define i64 @test_bextr_u64(i64 %a0, i32 %a1, i32 %a2) { 136; X64-LABEL: test_bextr_u64: 137; X64: # %bb.0: 138; X64-NEXT: andl $255, %esi 139; X64-NEXT: andl $255, %edx 140; X64-NEXT: shll $8, %edx 141; X64-NEXT: orl %esi, %edx 142; X64-NEXT: movl %edx, %eax 143; X64-NEXT: bextrq %rax, %rdi, %rax 144; X64-NEXT: retq 145; 146; EGPR-LABEL: test_bextr_u64: 147; EGPR: # %bb.0: 148; EGPR-NEXT: andl $255, %esi # encoding: [0x81,0xe6,0xff,0x00,0x00,0x00] 149; EGPR-NEXT: andl $255, %edx # encoding: [0x81,0xe2,0xff,0x00,0x00,0x00] 150; EGPR-NEXT: shll $8, %edx # encoding: [0xc1,0xe2,0x08] 151; EGPR-NEXT: orl %esi, %edx # encoding: [0x09,0xf2] 152; EGPR-NEXT: movl %edx, %eax # encoding: [0x89,0xd0] 153; EGPR-NEXT: bextrq %rax, %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf8,0xf7,0xc7] 154; EGPR-NEXT: retq # encoding: [0xc3] 155 %and1 = and i32 %a1, 255 156 %and2 = and i32 %a2, 255 157 %shl = shl i32 %and2, 8 158 %or = or i32 %and1, %shl 159 %zext = zext i32 %or to i64 160 %res = call i64 @llvm.x86.bmi.bextr.64(i64 %a0, i64 %zext) 161 ret i64 %res 162} 163 164define i64 @test_blsi_u64(i64 %a0) { 165; X64-LABEL: test_blsi_u64: 166; X64: # %bb.0: 167; X64-NEXT: xorl %eax, %eax 168; X64-NEXT: subq %rdi, %rax 169; X64-NEXT: andq %rdi, %rax 170; X64-NEXT: retq 171; 172; EGPR-LABEL: test_blsi_u64: 173; EGPR: # %bb.0: 174; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] 175; EGPR-NEXT: subq %rdi, %rax # encoding: [0x48,0x29,0xf8] 176; EGPR-NEXT: andq %rdi, %rax # encoding: [0x48,0x21,0xf8] 177; EGPR-NEXT: retq # encoding: [0xc3] 178 %neg = sub i64 0, %a0 179 %res = and i64 %a0, %neg 180 ret i64 %res 181} 182 183define i64 @test_blsmsk_u64(i64 %a0) { 184; X64-LABEL: test_blsmsk_u64: 185; X64: # %bb.0: 186; X64-NEXT: leaq -1(%rdi), %rax 187; X64-NEXT: xorq %rdi, %rax 188; X64-NEXT: retq 189; 190; EGPR-LABEL: test_blsmsk_u64: 191; EGPR: # %bb.0: 192; EGPR-NEXT: leaq -1(%rdi), %rax # encoding: [0x48,0x8d,0x47,0xff] 193; EGPR-NEXT: xorq %rdi, %rax # encoding: [0x48,0x31,0xf8] 194; EGPR-NEXT: retq # encoding: [0xc3] 195 %dec = sub i64 %a0, 1 196 %res = xor i64 %a0, %dec 197 ret i64 %res 198} 199 200define i64 @test_blsr_u64(i64 %a0) { 201; X64-LABEL: test_blsr_u64: 202; X64: # %bb.0: 203; X64-NEXT: leaq -1(%rdi), %rax 204; X64-NEXT: andq %rdi, %rax 205; X64-NEXT: retq 206; 207; EGPR-LABEL: test_blsr_u64: 208; EGPR: # %bb.0: 209; EGPR-NEXT: leaq -1(%rdi), %rax # encoding: [0x48,0x8d,0x47,0xff] 210; EGPR-NEXT: andq %rdi, %rax # encoding: [0x48,0x21,0xf8] 211; EGPR-NEXT: retq # encoding: [0xc3] 212 %dec = sub i64 %a0, 1 213 %res = and i64 %a0, %dec 214 ret i64 %res 215} 216 217define i64 @test_tzcnt_u64(i64 %a0) { 218; X64-LABEL: test_tzcnt_u64: 219; X64: # %bb.0: 220; X64-NEXT: tzcntq %rdi, %rax 221; X64-NEXT: retq 222; 223; EGPR-LABEL: test_tzcnt_u64: 224; EGPR: # %bb.0: 225; EGPR-NEXT: tzcntq %rdi, %rax # encoding: [0xf3,0x48,0x0f,0xbc,0xc7] 226; EGPR-NEXT: retq # encoding: [0xc3] 227 %cmp = icmp ne i64 %a0, 0 228 %cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 false) 229 ret i64 %cttz 230} 231 232declare i64 @llvm.cttz.i64(i64, i1) 233declare i64 @llvm.x86.bmi.bextr.64(i64, i64) 234