1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx | FileCheck %s 3 4@x = common global <8 x float> zeroinitializer, align 32 5@y = common global <4 x double> zeroinitializer, align 32 6@z = common global <4 x float> zeroinitializer, align 16 7 8define void @zero128() nounwind ssp { 9; CHECK-LABEL: zero128: 10; CHECK: ## %bb.0: 11; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 12; CHECK-NEXT: movq _z@GOTPCREL(%rip), %rax 13; CHECK-NEXT: vmovaps %xmm0, (%rax) 14; CHECK-NEXT: retq 15 store <4 x float> zeroinitializer, ptr @z, align 16 16 ret void 17} 18 19define void @zero256() nounwind ssp { 20; CHECK-LABEL: zero256: 21; CHECK: ## %bb.0: 22; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 23; CHECK-NEXT: movq _x@GOTPCREL(%rip), %rax 24; CHECK-NEXT: vmovaps %ymm0, (%rax) 25; CHECK-NEXT: movq _y@GOTPCREL(%rip), %rax 26; CHECK-NEXT: vmovaps %ymm0, (%rax) 27; CHECK-NEXT: vzeroupper 28; CHECK-NEXT: retq 29 store <8 x float> zeroinitializer, ptr @x, align 32 30 store <4 x double> zeroinitializer, ptr @y, align 32 31 ret void 32} 33 34define void @ones(ptr nocapture %RET, ptr nocapture %aFOO) nounwind { 35; CHECK-LABEL: ones: 36; CHECK: ## %bb.0: ## %allocas 37; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 38; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 39; CHECK-NEXT: vmovaps %ymm0, (%rdi) 40; CHECK-NEXT: vzeroupper 41; CHECK-NEXT: retq 42allocas: 43 store <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 440xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 450xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, ptr %RET, align 32 46 ret void 47} 48 49define void @ones2(ptr nocapture %RET, ptr nocapture %aFOO) nounwind { 50; CHECK-LABEL: ones2: 51; CHECK: ## %bb.0: ## %allocas 52; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 53; CHECK-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0 54; CHECK-NEXT: vmovaps %ymm0, (%rdi) 55; CHECK-NEXT: vzeroupper 56; CHECK-NEXT: retq 57allocas: 58 store <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, ptr %RET, align 32 59 ret void 60} 61 62;;; Just make sure this doesn't crash 63define <4 x i64> @ISelCrash(<4 x i64> %a) nounwind uwtable readnone ssp { 64; CHECK-LABEL: ISelCrash: 65; CHECK: ## %bb.0: 66; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0 67; CHECK-NEXT: retq 68 %shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 4> 69 ret <4 x i64> %shuffle 70} 71 72;;; Don't crash on movd 73define <8 x i32> @VMOVZQI2PQI(ptr nocapture %aFOO) nounwind { 74; CHECK-LABEL: VMOVZQI2PQI: 75; CHECK: ## %bb.0: 76; CHECK-NEXT: vbroadcastss (%rdi), %ymm0 77; CHECK-NEXT: retq 78 %val.i34.i = load i32, ptr %aFOO, align 4 79 %ptroffset.i22.i992 = getelementptr [0 x float], ptr %aFOO, i64 0, i64 1 80 %val.i24.i = load i32, ptr %ptroffset.i22.i992, align 4 81 %updatedret.i30.i = insertelement <8 x i32> undef, i32 %val.i34.i, i32 1 82 ret <8 x i32> %updatedret.i30.i 83} 84 85;;;; Don't crash on fneg 86; rdar://10566486 87define <16 x float> @fneg(<16 x float> %a) nounwind { 88; CHECK-LABEL: fneg: 89; CHECK: ## %bb.0: 90; CHECK-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] 91; CHECK-NEXT: vxorps %ymm2, %ymm0, %ymm0 92; CHECK-NEXT: vxorps %ymm2, %ymm1, %ymm1 93; CHECK-NEXT: retq 94 %1 = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a 95 ret <16 x float> %1 96} 97 98;;; Don't crash on build vector 99define <16 x i16> @build_vec_16x16(i16 %a) nounwind readonly { 100; CHECK-LABEL: build_vec_16x16: 101; CHECK: ## %bb.0: 102; CHECK-NEXT: movzwl %di, %eax 103; CHECK-NEXT: vmovd %eax, %xmm0 104; CHECK-NEXT: retq 105 %res = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %a, i32 0 106 ret <16 x i16> %res 107} 108 109;;; Check that VMOVPQIto64rr generates the assembly string "vmovq". Previously 110;;; an incorrect mnemonic of "movd" was printed for this instruction. 111define i64 @VMOVPQIto64rr(<2 x i64> %a) { 112; CHECK-LABEL: VMOVPQIto64rr: 113; CHECK: ## %bb.0: 114; CHECK-NEXT: vmovq %xmm0, %rax 115; CHECK-NEXT: retq 116 %vecext.i = extractelement <2 x i64> %a, i32 0 117 ret i64 %vecext.i 118} 119 120; PR22685 121define <8 x float> @mov00_8f32(ptr %ptr) { 122; CHECK-LABEL: mov00_8f32: 123; CHECK: ## %bb.0: 124; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero 125; CHECK-NEXT: retq 126 %val = load float, ptr %ptr 127 %vec = insertelement <8 x float> zeroinitializer, float %val, i32 0 128 ret <8 x float> %vec 129} 130