1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64 -mattr=+zu | FileCheck %s 3 4define i16 @i8(i8 %x) nounwind { 5; CHECK-LABEL: i8: 6; CHECK: # %bb.0: 7; CHECK-NEXT: cmpb $3, %dil 8; CHECK-NEXT: setzuae %al 9; CHECK-NEXT: # kill: def $ax killed $ax killed $eax 10; CHECK-NEXT: retq 11 %t0 = icmp ugt i8 %x, 2 12 %zext = zext i1 %t0 to i16 13 ret i16 %zext 14} 15 16define i16 @i16(i16 %x) nounwind { 17; CHECK-LABEL: i16: 18; CHECK: # %bb.0: 19; CHECK-NEXT: cmpw $2, %di 20; CHECK-NEXT: setzub %al 21; CHECK-NEXT: # kill: def $ax killed $ax killed $eax 22; CHECK-NEXT: retq 23 %t0 = icmp ult i16 %x, 2 24 %if = select i1 %t0, i16 1, i16 0 25 ret i16 %if 26} 27 28define i32 @i32(i32 %x) nounwind { 29; CHECK-LABEL: i32: 30; CHECK: # %bb.0: 31; CHECK-NEXT: cmpl $1, %edi 32; CHECK-NEXT: setzue %al 33; CHECK-NEXT: retq 34 %t0 = icmp eq i32 %x, 1 35 %if = select i1 %t0, i32 1, i32 0 36 ret i32 %if 37} 38 39define i64 @i64(i64 %x) nounwind { 40; CHECK-LABEL: i64: 41; CHECK: # %bb.0: 42; CHECK-NEXT: cmpq $1, %rdi 43; CHECK-NEXT: setzune %al 44; CHECK-NEXT: retq 45 %t0 = icmp ne i64 %x, 1 46 %if = select i1 %t0, i64 1, i64 0 47 ret i64 %if 48} 49 50define i32 @flags_copy_lowering() nounwind { 51; CHECK-LABEL: flags_copy_lowering: 52; CHECK: # %bb.0: # %bb 53; CHECK-NEXT: xorl %eax, %eax 54; CHECK-NEXT: xorl %edx, %edx 55; CHECK-NEXT: xorl %ecx, %ecx 56; CHECK-NEXT: .p2align 4 57; CHECK-NEXT: .LBB4_1: # %bb1 58; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 59; CHECK-NEXT: addl %edx, 0 60; CHECK-NEXT: setb %sil 61; CHECK-NEXT: adcl $0, %ecx 62; CHECK-NEXT: testb %sil, %sil 63; CHECK-NEXT: setzune %dl 64; CHECK-NEXT: testb %sil, %sil 65; CHECK-NEXT: je .LBB4_3 66; CHECK-NEXT: # %bb.2: # %bb1 67; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1 68; CHECK-NEXT: testb %al, %al 69; CHECK-NEXT: jne .LBB4_1 70; CHECK-NEXT: .LBB4_3: # %bb2 71; CHECK-NEXT: xorl %eax, %eax 72; CHECK-NEXT: retq 73bb: 74 br label %bb1 75 76bb1: 77 %phi = phi i32 [ 0, %bb ], [ %zext, %bb1 ] 78 %phi2 = phi i32 [ 0, %bb ], [ %add3, %bb1 ] 79 %load = load i32, ptr null, align 4 80 %add = add i32 %load, %phi 81 store i32 %add, ptr null, align 4 82 %icmp = icmp ugt i32 %phi, %add 83 %zext = zext i1 %icmp to i32 84 %add3 = add i32 %phi2, %zext 85 %icmp4 = icmp ult i32 %phi2, 0 86 %and = and i1 %icmp, false 87 br i1 %and, label %bb1, label %bb2 88 89bb2: 90 ret i32 0 91} 92