1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+egpr -show-mc-encoding | FileCheck --check-prefix=AVX512 %s 3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512bw,+egpr -show-mc-encoding | FileCheck --check-prefix=AVX512BW %s 4 5define void @kmovkr_1(i1 %cmp23.not) { 6; AVX512-LABEL: kmovkr_1: 7; AVX512: # %bb.0: # %entry 8; AVX512-NEXT: kmovw %edi, %k1 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x92,0xcf] 9; AVX512-NEXT: vmovsd {{.*#+}} xmm0 {%k1} {z} = [1.0E+0,0.0E+0] 10; AVX512-NEXT: # encoding: [0x62,0xf1,0xff,0x89,0x10,0x05,A,A,A,A] 11; AVX512-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte 12; AVX512-NEXT: vmovsd %xmm0, 0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x11,0x04,0x25,0x00,0x00,0x00,0x00] 13; AVX512-NEXT: retq # encoding: [0xc3] 14; 15; AVX512BW-LABEL: kmovkr_1: 16; AVX512BW: # %bb.0: # %entry 17; AVX512BW-NEXT: kmovd %edi, %k1 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x92,0xcf] 18; AVX512BW-NEXT: vmovsd {{.*#+}} xmm0 {%k1} {z} = [1.0E+0,0.0E+0] 19; AVX512BW-NEXT: # encoding: [0x62,0xf1,0xff,0x89,0x10,0x05,A,A,A,A] 20; AVX512BW-NEXT: # fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte 21; AVX512BW-NEXT: vmovsd %xmm0, 0 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x11,0x04,0x25,0x00,0x00,0x00,0x00] 22; AVX512BW-NEXT: retq # encoding: [0xc3] 23entry: 24 %0 = select i1 %cmp23.not, double 1.000000e+00, double 0.000000e+00 25 store double %0, ptr null, align 8 26 ret void 27} 28 29define void @kmovkr_2() { 30; AVX512-LABEL: kmovkr_2: 31; AVX512: # %bb.0: # %alloca_21 32; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0] 33; AVX512-NEXT: movw $3, %ax # encoding: [0x66,0xb8,0x03,0x00] 34; AVX512-NEXT: kmovw %eax, %k1 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x92,0xc8] 35; AVX512-NEXT: vmovups %zmm0, 0 {%k1} # encoding: [0x62,0xf1,0x7c,0x49,0x11,0x04,0x25,0x00,0x00,0x00,0x00] 36; AVX512-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 37; AVX512-NEXT: retq # encoding: [0xc3] 38; 39; AVX512BW-LABEL: kmovkr_2: 40; AVX512BW: # %bb.0: # %alloca_21 41; AVX512BW-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0] 42; AVX512BW-NEXT: movw $3, %ax # encoding: [0x66,0xb8,0x03,0x00] 43; AVX512BW-NEXT: kmovd %eax, %k1 # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x92,0xc8] 44; AVX512BW-NEXT: vmovups %zmm0, 0 {%k1} # encoding: [0x62,0xf1,0x7c,0x49,0x11,0x04,0x25,0x00,0x00,0x00,0x00] 45; AVX512BW-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 46; AVX512BW-NEXT: retq # encoding: [0xc3] 47alloca_21: 48 call void @llvm.masked.store.v4f32.p0(<4 x float> zeroinitializer, ptr null, i32 1, <4 x i1> <i1 true, i1 true, i1 false, i1 false>) 49 ret void 50} 51 52define i32 @kmovrk_1(<4 x ptr> %arg) { 53; AVX512-LABEL: kmovrk_1: 54; AVX512: # %bb.0: # %bb 55; AVX512-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] 56; AVX512-NEXT: jne .LBB2_1 # encoding: [0x75,A] 57; AVX512-NEXT: # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1 58; AVX512-NEXT: # %bb.2: # %bb3 59; AVX512-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] 60; AVX512-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 61; AVX512-NEXT: retq # encoding: [0xc3] 62; AVX512-NEXT: .LBB2_1: # %bb2 63; 64; AVX512BW-LABEL: kmovrk_1: 65; AVX512BW: # %bb.0: # %bb 66; AVX512BW-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] 67; AVX512BW-NEXT: jne .LBB2_1 # encoding: [0x75,A] 68; AVX512BW-NEXT: # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1 69; AVX512BW-NEXT: # %bb.2: # %bb3 70; AVX512BW-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] 71; AVX512BW-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] 72; AVX512BW-NEXT: retq # encoding: [0xc3] 73; AVX512BW-NEXT: .LBB2_1: # %bb2 74bb: 75 %icmp = icmp ne <4 x ptr> %arg, zeroinitializer 76 %freeze = freeze <4 x i1> %icmp 77 %bitcast = bitcast <4 x i1> %freeze to i4 78 %icmp1 = icmp ne i4 %bitcast, 0 79 br i1 %icmp1, label %bb2, label %bb3 80bb2: 81 unreachable 82bb3: 83 ret i32 0 84} 85 86declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr nocapture, i32 immarg, <4 x i1>) 87