xref: /llvm-project/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir (revision d1a0605337acf25eeda68a6fc6d5f7891d5bf813) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2# RUN: llc  -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD %s
3# RUN: llc  -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD-NF %s
4# Lower various interesting copy patterns of EFLAGS without using LAHF/SAHF.
5
6...
7---
8name:            test_adc
9body:             |
10  bb.0:
11    liveins: $rdi, $rsi
12
13    ; CHECK-LABEL: name: test_adc
14    ; CHECK: liveins: $rdi, $rsi
15    ; CHECK-NEXT: {{  $}}
16    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
17    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
18    ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
19    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
20    ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
21    ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
22    ; CHECK-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
23    ; CHECK-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
24    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
25    ; CHECK-NEXT: RET 0
26    %0:gr64 = COPY $rdi
27    %1:gr64 = COPY $rsi
28    %2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
29    %3:gr64 = COPY $eflags
30
31    INLINEASM &nop, 1, 12, implicit-def dead $eflags
32
33    $eflags = COPY %3
34    %4:gr64 = ADC64ri32_ND %2:gr64, 42, implicit-def $eflags, implicit $eflags
35    %5:gr64 = ADC64ri32_ND %4:gr64, 42, implicit-def $eflags, implicit $eflags
36    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
37
38    RET 0
39
40...
41---
42name:            test_sbb
43body:             |
44  bb.0:
45    liveins: $rdi, $rsi
46
47    ; CHECK-LABEL: name: test_sbb
48    ; CHECK: liveins: $rdi, $rsi
49    ; CHECK-NEXT: {{  $}}
50    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
51    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
52    ; CHECK-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
53    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
54    ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
55    ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
56    ; CHECK-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
57    ; CHECK-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
58    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
59    ; CHECK-NEXT: RET 0
60    %0:gr64 = COPY $rdi
61    %1:gr64 = COPY $rsi
62    %2:gr64 = SUB64rr_ND %0, %1, implicit-def $eflags
63    %3:gr64 = COPY killed $eflags
64
65    INLINEASM &nop, 1, 12, implicit-def dead $eflags
66
67    $eflags = COPY %3
68    %4:gr64 = SBB64ri32_ND %2:gr64, 42, implicit-def $eflags, implicit killed $eflags
69    %5:gr64 = SBB64ri32_ND %4:gr64, 42, implicit-def dead $eflags, implicit killed $eflags
70    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
71
72    RET 0
73
74...
75---
76name:            test_rcl
77body:             |
78  bb.0:
79    liveins: $rdi, $rsi
80
81    ; CHECK-LABEL: name: test_rcl
82    ; CHECK: liveins: $rdi, $rsi
83    ; CHECK-NEXT: {{  $}}
84    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
85    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
86    ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
87    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
88    ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
89    ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
90    ; CHECK-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
91    ; CHECK-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
92    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
93    ; CHECK-NEXT: RET 0
94    %0:gr64 = COPY $rdi
95    %1:gr64 = COPY $rsi
96    %2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
97    %3:gr64 = COPY $eflags
98
99    INLINEASM &nop, 1, 12, implicit-def dead $eflags
100
101    $eflags = COPY %3
102    %4:gr64 = RCL64r1_ND %2:gr64, implicit-def $eflags, implicit $eflags
103    %5:gr64 = RCL64r1_ND %4:gr64, implicit-def $eflags, implicit $eflags
104    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
105
106    RET 0
107
108...
109---
110name:            test_rcr
111body:             |
112  bb.0:
113    liveins: $rdi, $rsi
114
115    ; CHECK-LABEL: name: test_rcr
116    ; CHECK: liveins: $rdi, $rsi
117    ; CHECK-NEXT: {{  $}}
118    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
119    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
120    ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
121    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
122    ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
123    ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
124    ; CHECK-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
125    ; CHECK-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
126    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
127    ; CHECK-NEXT: RET 0
128    %0:gr64 = COPY $rdi
129    %1:gr64 = COPY $rsi
130    %2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
131    %3:gr64 = COPY $eflags
132
133    INLINEASM &nop, 1, 12, implicit-def dead $eflags
134
135    $eflags = COPY %3
136    %4:gr64 = RCR64r1_ND %2:gr64, implicit-def $eflags, implicit $eflags
137    %5:gr64 = RCR64r1_ND %4:gr64, implicit-def $eflags, implicit $eflags
138    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
139
140    RET 0
141
142...
143---
144name:            test_cmov
145body:             |
146  bb.0:
147    liveins: $rdi, $rsi
148
149    ; CHECK-LABEL: name: test_cmov
150    ; CHECK: liveins: $rdi, $rsi
151    ; CHECK-NEXT: {{  $}}
152    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
153    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
154    ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
155    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
156    ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
157    ; CHECK-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
158    ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
159    ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
160    ; CHECK-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
161    ; CHECK-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
162    ; CHECK-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
163    ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
164    ; CHECK-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
165    ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
166    ; CHECK-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
167    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
168    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
169    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
170    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
171    ; CHECK-NEXT: RET 0
172    %0:gr64 = COPY $rdi
173    %1:gr64 = COPY $rsi
174    CMP64rr %0, %1, implicit-def $eflags
175    %2:gr64 = COPY $eflags
176
177    INLINEASM &nop, 1, 12, implicit-def dead $eflags
178
179    $eflags = COPY %2
180    %3:gr64 = CMOV64rr_ND %0, %1, 7, implicit $eflags
181    %4:gr64 = CMOV64rr_ND %0, %1, 2, implicit $eflags
182    %5:gr64 = CMOV64rr_ND %0, %1, 4, implicit $eflags
183    %6:gr64 = CMOV64rr_ND %0, %1, 5, implicit killed $eflags
184    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %3
185    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %4
186    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
187    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %6
188
189    RET 0
190...
191---
192name:            test_cfcmov
193body:             |
194  bb.0:
195    liveins: $rdi, $rsi
196
197    ; CHECK-LABEL: name: test_cfcmov
198    ; CHECK: liveins: $rdi, $rsi
199    ; CHECK-NEXT: {{  $}}
200    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
201    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
202    ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
203    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
204    ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
205    ; CHECK-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
206    ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
207    ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
208    ; CHECK-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
209    ; CHECK-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
210    ; CHECK-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
211    ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
212    ; CHECK-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
213    ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
214    ; CHECK-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
215    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
216    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
217    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
218    ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
219    ; CHECK-NEXT: RET 0
220    %0:gr64 = COPY $rdi
221    %1:gr64 = COPY $rsi
222    CMP64rr %0, %1, implicit-def $eflags
223    %2:gr64 = COPY $eflags
224
225    INLINEASM &nop, 1, 12, implicit-def dead $eflags
226
227    $eflags = COPY %2
228    %3:gr64 = CFCMOV64rr %1, 7, implicit $eflags
229    %4:gr64 = CFCMOV64rr %1, 2, implicit $eflags
230    %5:gr64 = CFCMOV64rr_ND %0, %1, 4, implicit $eflags
231    %6:gr64 = CFCMOV64rr_ND %0, %1, 5, implicit killed $eflags
232    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %3
233    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %4
234    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %5
235    MOV64mr $rsp, 1, $noreg, -16, $noreg, killed %6
236
237    RET 0
238...
239---
240name:            test_ccmp
241body:             |
242  bb.0:
243    liveins: $edi
244
245    ; NDD-LABEL: name: test_ccmp
246    ; NDD: liveins: $edi
247    ; NDD-NEXT: {{  $}}
248    ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
249    ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 1, implicit $eflags
250    ; NDD-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
251    ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
252    ; NDD-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
253    ; NDD-NEXT: RET 0, $al
254    ;
255    ; NDD-NF-LABEL: name: test_ccmp
256    ; NDD-NF: liveins: $edi
257    ; NDD-NF-NEXT: {{  $}}
258    ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
259    ; NDD-NF-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
260    ; NDD-NF-NEXT: CCMP32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
261    ; NDD-NF-NEXT: RET 0, $al
262    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
263    %1:gr64 = COPY $eflags
264    %2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
265    $eflags = COPY %1
266    CCMP32rr %2, %2, 0, 1, implicit-def $eflags, implicit $eflags
267    RET 0, $al
268
269...
270---
271name:            test_ctest
272body:             |
273  bb.0:
274    liveins: $edi
275
276    ; NDD-LABEL: name: test_ctest
277    ; NDD: liveins: $edi
278    ; NDD-NEXT: {{  $}}
279    ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
280    ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 1, implicit $eflags
281    ; NDD-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
282    ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
283    ; NDD-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
284    ; NDD-NEXT: RET 0, $al
285    ;
286    ; NDD-NF-LABEL: name: test_ctest
287    ; NDD-NF: liveins: $edi
288    ; NDD-NF-NEXT: {{  $}}
289    ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
290    ; NDD-NF-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
291    ; NDD-NF-NEXT: CTEST32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
292    ; NDD-NF-NEXT: RET 0, $al
293    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
294    %1:gr64 = COPY $eflags
295    %2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
296    $eflags = COPY %1
297    CTEST32rr %2, %2, 0, 1, implicit-def $eflags, implicit $eflags
298    RET 0, $al
299
300...
301---
302name:            test_evitable_clobber
303body:             |
304  bb.0:
305    liveins: $edi
306
307    ; NDD-LABEL: name: test_evitable_clobber
308    ; NDD: liveins: $edi
309    ; NDD-NEXT: {{  $}}
310    ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
311    ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
312    ; NDD-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
313    ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
314    ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
315    ; NDD-NEXT: RET 0, $al
316    ;
317    ; NDD-NF-LABEL: name: test_evitable_clobber
318    ; NDD-NF: liveins: $edi
319    ; NDD-NF-NEXT: {{  $}}
320    ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
321    ; NDD-NF-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
322    ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
323    ; NDD-NF-NEXT: RET 0, $al
324    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
325    %1:gr64 = COPY $eflags
326    %2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
327    $eflags = COPY %1
328    $eax = CMOV32rr_ND $edi, %2, 7, implicit $eflags
329    RET 0, $al
330
331...
332---
333name:            test_inevitable_clobber
334body:             |
335  bb.0:
336    liveins: $edi
337
338    ; CHECK-LABEL: name: test_inevitable_clobber
339    ; CHECK: liveins: $edi
340    ; CHECK-NEXT: {{  $}}
341    ; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
342    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
343    ; CHECK-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
344    ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
345    ; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
346    ; CHECK-NEXT: RET 0, $al
347    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
348    %1:gr64 = COPY $eflags
349    %2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
350    $eflags = COPY %1
351    $eax = CMOV32rr_ND $edi, %2, 7, implicit $eflags
352    RET 0, $al
353...
354---
355name:            test_evitable_clobber_multiple_uses
356body:             |
357  bb.0:
358    liveins: $edi
359
360    ; NDD-LABEL: name: test_evitable_clobber_multiple_uses
361    ; NDD: liveins: $edi
362    ; NDD-NEXT: {{  $}}
363    ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
364    ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
365    ; NDD-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 9, implicit $eflags
366    ; NDD-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
367    ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
368    ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
369    ; NDD-NEXT: [[ADD32rr_ND1:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $eax, implicit-def dead $eflags
370    ; NDD-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
371    ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
372    ; NDD-NEXT: RET 0, $al
373    ;
374    ; NDD-NF-LABEL: name: test_evitable_clobber_multiple_uses
375    ; NDD-NF: liveins: $edi
376    ; NDD-NF-NEXT: {{  $}}
377    ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
378    ; NDD-NF-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
379    ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
380    ; NDD-NF-NEXT: [[ADD32rr_NF_ND1:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $eax
381    ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND1]], 9, implicit $eflags
382    ; NDD-NF-NEXT: RET 0, $al
383    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
384    %1:gr64 = COPY $eflags
385    %2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
386    $eflags = COPY %1
387    $eax = CMOV32rr_ND $edi, %2, 7, implicit $eflags
388    %3:gr32 = ADD32rr_ND $edi, $eax, implicit-def dead $eflags
389    $eflags = COPY %1
390    $eax = CMOV32rr_ND $edi, %3, 9, implicit $eflags
391    RET 0, $al
392
393...
394---
395name:            test_mixed_clobber
396body:             |
397  bb.0:
398    liveins: $edi
399
400    ; NDD-LABEL: name: test_mixed_clobber
401    ; NDD: liveins: $edi
402    ; NDD-NEXT: {{  $}}
403    ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
404    ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
405    ; NDD-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
406    ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
407    ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
408    ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
409    ; NDD-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 1, implicit $eflags
410    ; NDD-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
411    ; NDD-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
412    ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
413    ; NDD-NEXT: RET 0, $al
414    ;
415    ; NDD-NF-LABEL: name: test_mixed_clobber
416    ; NDD-NF: liveins: $edi
417    ; NDD-NF-NEXT: {{  $}}
418    ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
419    ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
420    ; NDD-NF-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
421    ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
422    ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
423    ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
424    ; NDD-NF-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
425    ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 1, implicit $eflags
426    ; NDD-NF-NEXT: RET 0, $al
427    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
428    %1:gr64 = COPY $eflags
429    %2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
430    $eflags = COPY %1
431    $eax = CMOV32rr_ND $edi, %2, 7, implicit $eflags
432    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
433    %3:gr64 = COPY $eflags
434    %4:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
435    $eflags = COPY %3
436    $eax = CMOV32rr_ND $edi, %4, 1, implicit $eflags
437    RET 0, $al
438...
439---
440name:            test_evitable_clobber_crossbb
441body:             |
442  ; NDD-LABEL: name: test_evitable_clobber_crossbb
443  ; NDD: bb.0:
444  ; NDD-NEXT:   successors: %bb.1(0x80000000)
445  ; NDD-NEXT:   liveins: $edi
446  ; NDD-NEXT: {{  $}}
447  ; NDD-NEXT:   MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
448  ; NDD-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
449  ; NDD-NEXT:   [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
450  ; NDD-NEXT:   [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
451  ; NDD-NEXT:   JCC_1 %bb.1, 4, implicit $eflags
452  ; NDD-NEXT:   RET 0, $al
453  ; NDD-NEXT: {{  $}}
454  ; NDD-NEXT: bb.1:
455  ; NDD-NEXT:   TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
456  ; NDD-NEXT:   $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
457  ; NDD-NEXT:   dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr1]], 255, implicit-def $eflags
458  ; NDD-NEXT:   $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
459  ; NDD-NEXT:   RET 0, $al
460  ;
461  ; NDD-NF-LABEL: name: test_evitable_clobber_crossbb
462  ; NDD-NF: bb.0:
463  ; NDD-NF-NEXT:   successors: %bb.1(0x80000000)
464  ; NDD-NF-NEXT:   liveins: $edi
465  ; NDD-NF-NEXT: {{  $}}
466  ; NDD-NF-NEXT:   MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
467  ; NDD-NF-NEXT:   [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
468  ; NDD-NF-NEXT:   JCC_1 %bb.1, 4, implicit $eflags
469  ; NDD-NF-NEXT:   RET 0, $al
470  ; NDD-NF-NEXT: {{  $}}
471  ; NDD-NF-NEXT: bb.1:
472  ; NDD-NF-NEXT:   liveins: $eflags
473  ; NDD-NF-NEXT: {{  $}}
474  ; NDD-NF-NEXT:   $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
475  ; NDD-NF-NEXT:   $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
476  ; NDD-NF-NEXT:   RET 0, $al
477  bb.0:
478    liveins: $edi
479
480    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
481    %1:gr64 = COPY $eflags
482    %2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
483    JCC_1 %bb.1, 4, implicit $eflags
484    RET 0, $al
485
486  bb.1:
487    $eflags = COPY %1
488    $eax = CMOV32rr_ND $edi, %2, 7, implicit $eflags
489    $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
490    RET 0, $al
491...
492---
493name:            test_inevitable_clobber_crossbb
494body:             |
495  ; CHECK-LABEL: name: test_inevitable_clobber_crossbb
496  ; CHECK: bb.0:
497  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
498  ; CHECK-NEXT:   liveins: $edi
499  ; CHECK-NEXT: {{  $}}
500  ; CHECK-NEXT:   MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
501  ; CHECK-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
502  ; CHECK-NEXT:   [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
503  ; CHECK-NEXT:   JCC_1 %bb.1, 4, implicit $eflags
504  ; CHECK-NEXT:   RET 0, $al
505  ; CHECK-NEXT: {{  $}}
506  ; CHECK-NEXT: bb.1:
507  ; CHECK-NEXT:   TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
508  ; CHECK-NEXT:   $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
509  ; CHECK-NEXT:   RET 0, $al
510  bb.0:
511    liveins: $edi
512
513    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
514    %1:gr64 = COPY $eflags
515    %2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
516    JCC_1 %bb.1, 4, implicit $eflags
517    RET 0, $al
518
519  bb.1:
520    $eflags = COPY %1
521    $eax = CMOV32rr_ND $edi, %2, 7, implicit $eflags
522    RET 0, $al
523...
524---
525name:            test_evitable_clobber_crossbb_complex
526body:             |
527  ; NDD-LABEL: name: test_evitable_clobber_crossbb_complex
528  ; NDD: bb.0:
529  ; NDD-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
530  ; NDD-NEXT:   liveins: $edi
531  ; NDD-NEXT: {{  $}}
532  ; NDD-NEXT:   MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
533  ; NDD-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
534  ; NDD-NEXT:   [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
535  ; NDD-NEXT:   JCC_1 %bb.2, 4, implicit $eflags
536  ; NDD-NEXT: {{  $}}
537  ; NDD-NEXT: bb.1:
538  ; NDD-NEXT:   successors: %bb.3(0x80000000)
539  ; NDD-NEXT: {{  $}}
540  ; NDD-NEXT:   $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
541  ; NDD-NEXT:   JMP_1 %bb.3
542  ; NDD-NEXT: {{  $}}
543  ; NDD-NEXT: bb.2:
544  ; NDD-NEXT:   successors: %bb.3(0x80000000)
545  ; NDD-NEXT: {{  $}}
546  ; NDD-NEXT:   $eax = IMUL32rr $eax, $esi, implicit-def dead $eflags
547  ; NDD-NEXT:   JMP_1 %bb.3
548  ; NDD-NEXT: {{  $}}
549  ; NDD-NEXT: bb.3:
550  ; NDD-NEXT:   TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
551  ; NDD-NEXT:   $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
552  ; NDD-NEXT:   RET 0, $al
553  ;
554  ; NDD-NF-LABEL: name: test_evitable_clobber_crossbb_complex
555  ; NDD-NF: bb.0:
556  ; NDD-NF-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
557  ; NDD-NF-NEXT:   liveins: $edi
558  ; NDD-NF-NEXT: {{  $}}
559  ; NDD-NF-NEXT:   MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
560  ; NDD-NF-NEXT:   [[SUB32rr_NF_ND:%[0-9]+]]:gr32 = SUB32rr_NF_ND $edi, $edi
561  ; NDD-NF-NEXT:   JCC_1 %bb.2, 4, implicit $eflags
562  ; NDD-NF-NEXT: {{  $}}
563  ; NDD-NF-NEXT: bb.1:
564  ; NDD-NF-NEXT:   successors: %bb.3(0x80000000)
565  ; NDD-NF-NEXT:   liveins: $eflags
566  ; NDD-NF-NEXT: {{  $}}
567  ; NDD-NF-NEXT:   $eax = IMUL32rr_NF_ND $eax, $edi
568  ; NDD-NF-NEXT:   JMP_1 %bb.3
569  ; NDD-NF-NEXT: {{  $}}
570  ; NDD-NF-NEXT: bb.2:
571  ; NDD-NF-NEXT:   successors: %bb.3(0x80000000)
572  ; NDD-NF-NEXT:   liveins: $eflags
573  ; NDD-NF-NEXT: {{  $}}
574  ; NDD-NF-NEXT:   $eax = IMUL32rr_NF $eax, $esi
575  ; NDD-NF-NEXT:   JMP_1 %bb.3
576  ; NDD-NF-NEXT: {{  $}}
577  ; NDD-NF-NEXT: bb.3:
578  ; NDD-NF-NEXT:   liveins: $eflags
579  ; NDD-NF-NEXT: {{  $}}
580  ; NDD-NF-NEXT:   $eax = CMOV32rr_ND $edi, [[SUB32rr_NF_ND]], 7, implicit $eflags
581  ; NDD-NF-NEXT:   RET 0, $al
582  bb.0:
583    liveins: $edi
584
585    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
586    %1:gr64 = COPY $eflags
587    %2:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
588    JCC_1 %bb.2, 4, implicit $eflags
589
590  bb.1:
591    $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
592    JMP_1 %bb.3
593
594  bb.2:
595    $eax = IMUL32rr $eax, $esi, implicit-def dead $eflags
596    JMP_1 %bb.3
597
598  bb.3:
599    $eflags = COPY %1
600    $eax = CMOV32rr_ND $edi, %2, 7, implicit $eflags
601    RET 0, $al
602...
603---
604name:            test_inevitable_clobber_crossbb_complex
605body:             |
606  ; CHECK-LABEL: name: test_inevitable_clobber_crossbb_complex
607  ; CHECK: bb.0:
608  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
609  ; CHECK-NEXT:   liveins: $edi
610  ; CHECK-NEXT: {{  $}}
611  ; CHECK-NEXT:   MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
612  ; CHECK-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
613  ; CHECK-NEXT:   [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
614  ; CHECK-NEXT:   JCC_1 %bb.2, 4, implicit $eflags
615  ; CHECK-NEXT: {{  $}}
616  ; CHECK-NEXT: bb.1:
617  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
618  ; CHECK-NEXT: {{  $}}
619  ; CHECK-NEXT:   $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
620  ; CHECK-NEXT:   JMP_1 %bb.3
621  ; CHECK-NEXT: {{  $}}
622  ; CHECK-NEXT: bb.2:
623  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
624  ; CHECK-NEXT: {{  $}}
625  ; CHECK-NEXT:   $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
626  ; CHECK-NEXT:   JMP_1 %bb.3
627  ; CHECK-NEXT: {{  $}}
628  ; CHECK-NEXT: bb.3:
629  ; CHECK-NEXT:   TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
630  ; CHECK-NEXT:   $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
631  ; CHECK-NEXT:   RET 0, $al
632  bb.0:
633    liveins: $edi
634
635    MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
636    %1:gr64 = COPY $eflags
637    %2:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
638    JCC_1 %bb.2, 4, implicit $eflags
639
640  bb.1:
641    $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
642    JMP_1 %bb.3
643
644  bb.2:
645    $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
646    JMP_1 %bb.3
647
648  bb.3:
649    $eflags = COPY %1
650    $eax = CMOV32rr_ND $edi, %2, 7, implicit $eflags
651    RET 0, $al
652...
653