1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: not llc -mtriple=x86_64 < %s >%t1 2>%t2 3; RUN: FileCheck %s <%t1 4; RUN: FileCheck %s <%t2 --check-prefix=ERR 5; RUN: not llc -mattr=+egpr -mtriple=x86_64 < %s >%t1 2>%t2 6; RUN: FileCheck %s <%t1 7; RUN: FileCheck %s <%t2 --check-prefix=ERR 8; RUN: not llc -mattr=+egpr,+inline-asm-use-gpr32 -mtriple=x86_64 < %s >%t1 2>%t2 9; RUN: FileCheck %s <%t1 10; RUN: FileCheck %s <%t2 --check-prefix=ERR 11 12; CHECK: addq %r8, %rax 13define void @constraint_jr_test() nounwind { 14entry: 15 %reg = alloca i64, align 8 16 %0 = load i64, ptr %reg, align 8 17 call void asm sideeffect "add $0, %rax", "^jr,~{rax},~{rbx},~{rbp},~{rcx},~{rdx},~{rdi},~{rsi},~{dirflag},~{fpsr},~{flags}"(i64 %0) 18 ret void 19} 20 21; ERR: error: inline assembly requires more registers than available 22define void @constraint_jr_test_err() nounwind { 23entry: 24 %reg = alloca i64, align 8 25 %0 = load i64, ptr %reg, align 8 26 call void asm sideeffect "add $0, %rax", "^jr,~{rax},~{rbx},~{rbp},~{rcx},~{rdx},~{rdi},~{rsi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"(i64 %0) 27 ret void 28} 29