1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 6 define i8 @zext_i1_to_i8(i1 %val) { 7 %res = zext i1 %val to i8 8 ret i8 %res 9 } 10 11 define i16 @zext_i1_to_i16(i1 %val) { 12 %res = zext i1 %val to i16 13 ret i16 %res 14 } 15 16 define i32 @zext_i1_to_i32(i1 %val) { 17 %res = zext i1 %val to i32 18 ret i32 %res 19 } 20 21 define i64 @zext_i1_to_i64(i1 %val) { 22 %res = zext i1 %val to i64 23 ret i64 %res 24 } 25 26 define i16 @zext_i8_to_i16(i8 %val) { 27 %res = zext i8 %val to i16 28 ret i16 %res 29 } 30 31 define i32 @zext_i8_to_i32(i8 %val) { 32 %res = zext i8 %val to i32 33 ret i32 %res 34 } 35 36 define i64 @zext_i8_to_i64(i8 %val) { 37 %res = zext i8 %val to i64 38 ret i64 %res 39 } 40 41 define i32 @zext_i16_to_i32(i16 %val) { 42 %res = zext i16 %val to i32 43 ret i32 %res 44 } 45 46 define i64 @zext_i16_to_i64(i16 %val) { 47 %res = zext i16 %val to i64 48 ret i64 %res 49 } 50 51 define i64 @zext_i32_to_i64(i32 %val) { 52 %res = zext i32 %val to i64 53 ret i64 %res 54 } 55 56... 57--- 58name: zext_i1_to_i8 59alignment: 16 60legalized: true 61regBankSelected: true 62tracksRegLiveness: true 63registers: 64 - { id: 0, class: _ } 65 - { id: 1, class: gpr } 66 - { id: 2, class: gpr } 67 - { id: 3, class: gpr } 68 - { id: 4, class: gpr } 69body: | 70 bb.1 (%ir-block.0): 71 liveins: $edi 72 73 ; CHECK-LABEL: name: zext_i1_to_i8 74 ; CHECK: liveins: $edi 75 ; CHECK-NEXT: {{ $}} 76 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 77 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit 78 ; CHECK-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def dead $eflags 79 ; CHECK-NEXT: $al = COPY [[AND8ri]] 80 ; CHECK-NEXT: RET 0, implicit $al 81 %1:gpr(s32) = COPY $edi 82 %3:gpr(s8) = G_CONSTANT i8 1 83 %4:gpr(s8) = G_TRUNC %1(s32) 84 %2:gpr(s8) = G_AND %4, %3 85 $al = COPY %2(s8) 86 RET 0, implicit $al 87 88... 89--- 90name: zext_i1_to_i16 91alignment: 16 92legalized: true 93regBankSelected: true 94tracksRegLiveness: true 95registers: 96 - { id: 0, class: _ } 97 - { id: 1, class: gpr } 98 - { id: 2, class: gpr } 99 - { id: 3, class: gpr } 100 - { id: 4, class: gpr } 101body: | 102 bb.1 (%ir-block.0): 103 liveins: $edi 104 105 ; CHECK-LABEL: name: zext_i1_to_i16 106 ; CHECK: liveins: $edi 107 ; CHECK-NEXT: {{ $}} 108 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 109 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit 110 ; CHECK-NEXT: [[AND16ri:%[0-9]+]]:gr16 = AND16ri [[COPY1]], 1, implicit-def dead $eflags 111 ; CHECK-NEXT: $ax = COPY [[AND16ri]] 112 ; CHECK-NEXT: RET 0, implicit $ax 113 %1:gpr(s32) = COPY $edi 114 %3:gpr(s16) = G_CONSTANT i16 1 115 %4:gpr(s16) = G_TRUNC %1(s32) 116 %2:gpr(s16) = G_AND %4, %3 117 $ax = COPY %2(s16) 118 RET 0, implicit $ax 119 120... 121--- 122name: zext_i1_to_i32 123alignment: 16 124legalized: true 125regBankSelected: true 126tracksRegLiveness: true 127registers: 128 - { id: 0, class: _ } 129 - { id: 1, class: gpr } 130 - { id: 2, class: gpr } 131 - { id: 3, class: gpr } 132 - { id: 4, class: gpr } 133body: | 134 bb.1 (%ir-block.0): 135 liveins: $edi 136 137 ; CHECK-LABEL: name: zext_i1_to_i32 138 ; CHECK: liveins: $edi 139 ; CHECK-NEXT: {{ $}} 140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 141 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY]], 1, implicit-def dead $eflags 142 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 143 ; CHECK-NEXT: RET 0, implicit $eax 144 %1:gpr(s32) = COPY $edi 145 %3:gpr(s32) = G_CONSTANT i32 1 146 %4:gpr(s32) = COPY %1(s32) 147 %2:gpr(s32) = G_AND %4, %3 148 $eax = COPY %2(s32) 149 RET 0, implicit $eax 150 151... 152--- 153name: zext_i1_to_i64 154alignment: 16 155legalized: true 156regBankSelected: true 157tracksRegLiveness: true 158registers: 159 - { id: 0, class: _ } 160 - { id: 1, class: gpr } 161 - { id: 2, class: gpr } 162 - { id: 3, class: gpr } 163 - { id: 4, class: gpr } 164body: | 165 bb.1 (%ir-block.0): 166 liveins: $edi 167 168 ; CHECK-LABEL: name: zext_i1_to_i64 169 ; CHECK: liveins: $edi 170 ; CHECK-NEXT: {{ $}} 171 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 172 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF 173 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit 174 ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def dead $eflags 175 ; CHECK-NEXT: $rax = COPY [[AND64ri32_]] 176 ; CHECK-NEXT: RET 0, implicit $rax 177 %1:gpr(s32) = COPY $edi 178 %3:gpr(s64) = G_CONSTANT i64 1 179 %4:gpr(s64) = G_ANYEXT %1(s32) 180 %2:gpr(s64) = G_AND %4, %3 181 $rax = COPY %2(s64) 182 RET 0, implicit $rax 183 184... 185--- 186name: zext_i8_to_i16 187alignment: 16 188legalized: true 189regBankSelected: true 190tracksRegLiveness: true 191registers: 192 - { id: 0, class: _ } 193 - { id: 1, class: gpr } 194 - { id: 2, class: gpr } 195 - { id: 3, class: gpr } 196 - { id: 4, class: gpr } 197body: | 198 bb.1 (%ir-block.0): 199 liveins: $edi 200 201 ; CHECK-LABEL: name: zext_i8_to_i16 202 ; CHECK: liveins: $edi 203 ; CHECK-NEXT: {{ $}} 204 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 205 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit 206 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit 207 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]] 208 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit 209 ; CHECK-NEXT: $ax = COPY [[COPY3]] 210 ; CHECK-NEXT: RET 0, implicit $ax 211 %1:gpr(s32) = COPY $edi 212 %3:gpr(s16) = G_CONSTANT i16 255 213 %4:gpr(s16) = G_TRUNC %1(s32) 214 %2:gpr(s16) = G_AND %4, %3 215 $ax = COPY %2(s16) 216 RET 0, implicit $ax 217 218... 219--- 220name: zext_i8_to_i32 221alignment: 16 222legalized: true 223regBankSelected: true 224tracksRegLiveness: true 225registers: 226 - { id: 0, class: _ } 227 - { id: 1, class: gpr } 228 - { id: 2, class: gpr } 229 - { id: 3, class: gpr } 230 - { id: 4, class: gpr } 231body: | 232 bb.1 (%ir-block.0): 233 liveins: $edi 234 235 ; CHECK-LABEL: name: zext_i8_to_i32 236 ; CHECK: liveins: $edi 237 ; CHECK-NEXT: {{ $}} 238 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 239 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit 240 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] 241 ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]] 242 ; CHECK-NEXT: RET 0, implicit $eax 243 %1:gpr(s32) = COPY $edi 244 %3:gpr(s32) = G_CONSTANT i32 255 245 %4:gpr(s32) = COPY %1(s32) 246 %2:gpr(s32) = G_AND %4, %3 247 $eax = COPY %2(s32) 248 RET 0, implicit $eax 249 250... 251--- 252name: zext_i8_to_i64 253alignment: 16 254legalized: true 255regBankSelected: true 256tracksRegLiveness: true 257registers: 258 - { id: 0, class: _ } 259 - { id: 1, class: gpr } 260 - { id: 2, class: gpr } 261 - { id: 3, class: gpr } 262 - { id: 4, class: gpr } 263body: | 264 bb.1 (%ir-block.0): 265 liveins: $edi 266 267 ; CHECK-LABEL: name: zext_i8_to_i64 268 ; CHECK: liveins: $edi 269 ; CHECK-NEXT: {{ $}} 270 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 271 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF 272 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit 273 ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def dead $eflags 274 ; CHECK-NEXT: $rax = COPY [[AND64ri32_]] 275 ; CHECK-NEXT: RET 0, implicit $rax 276 %1:gpr(s32) = COPY $edi 277 %3:gpr(s64) = G_CONSTANT i64 255 278 %4:gpr(s64) = G_ANYEXT %1(s32) 279 %2:gpr(s64) = G_AND %4, %3 280 $rax = COPY %2(s64) 281 RET 0, implicit $rax 282 283... 284--- 285name: zext_i16_to_i32 286alignment: 16 287legalized: true 288regBankSelected: true 289tracksRegLiveness: true 290registers: 291 - { id: 0, class: _ } 292 - { id: 1, class: gpr } 293 - { id: 2, class: gpr } 294 - { id: 3, class: gpr } 295 - { id: 4, class: gpr } 296body: | 297 bb.1 (%ir-block.0): 298 liveins: $edi 299 300 ; CHECK-LABEL: name: zext_i16_to_i32 301 ; CHECK: liveins: $edi 302 ; CHECK-NEXT: {{ $}} 303 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 304 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit 305 ; CHECK-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]] 306 ; CHECK-NEXT: $eax = COPY [[MOVZX32rr16_]] 307 ; CHECK-NEXT: RET 0, implicit $eax 308 %1:gpr(s32) = COPY $edi 309 %3:gpr(s32) = G_CONSTANT i32 65535 310 %4:gpr(s32) = COPY %1(s32) 311 %2:gpr(s32) = G_AND %4, %3 312 $eax = COPY %2(s32) 313 RET 0, implicit $eax 314 315... 316--- 317name: zext_i16_to_i64 318alignment: 16 319legalized: true 320regBankSelected: true 321tracksRegLiveness: true 322registers: 323 - { id: 0, class: _ } 324 - { id: 1, class: gpr } 325 - { id: 2, class: gpr } 326 - { id: 3, class: gpr } 327 - { id: 4, class: gpr } 328body: | 329 bb.1 (%ir-block.0): 330 liveins: $edi 331 332 ; CHECK-LABEL: name: zext_i16_to_i64 333 ; CHECK: liveins: $edi 334 ; CHECK-NEXT: {{ $}} 335 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 336 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF 337 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit 338 ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def dead $eflags 339 ; CHECK-NEXT: $rax = COPY [[AND64ri32_]] 340 ; CHECK-NEXT: RET 0, implicit $rax 341 %1:gpr(s32) = COPY $edi 342 %3:gpr(s64) = G_CONSTANT i64 65535 343 %4:gpr(s64) = G_ANYEXT %1(s32) 344 %2:gpr(s64) = G_AND %4, %3 345 $rax = COPY %2(s64) 346 RET 0, implicit $rax 347 348... 349--- 350name: zext_i32_to_i64 351alignment: 16 352legalized: true 353regBankSelected: true 354tracksRegLiveness: true 355registers: 356 - { id: 0, class: gpr } 357 - { id: 1, class: gpr } 358body: | 359 bb.1 (%ir-block.0): 360 liveins: $edi 361 362 ; CHECK-LABEL: name: zext_i32_to_i64 363 ; CHECK: liveins: $edi 364 ; CHECK-NEXT: {{ $}} 365 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 366 ; CHECK-NEXT: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]] 367 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit 368 ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] 369 ; CHECK-NEXT: RET 0, implicit $rax 370 %0:gpr(s32) = COPY $edi 371 %1:gpr(s64) = G_ZEXT %0(s32) 372 $rax = COPY %1(s64) 373 RET 0, implicit $rax 374 375... 376