1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 ; ModuleID = 'sitofp_legal.ll' 6 source_filename = "sitofp.c" 7 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 8 target triple = "x86_64-unknown-linux-gnu" 9 10 ; Function Attrs: norecurse nounwind readnone uwtable 11 define dso_local float @int32_to_float(i32 %a) local_unnamed_addr #0 { 12 entry: 13 %conv = sitofp i32 %a to float 14 ret float %conv 15 } 16 17 ; Function Attrs: norecurse nounwind readnone uwtable 18 define dso_local float @int64_to_float(i64 %a) local_unnamed_addr #0 { 19 entry: 20 %conv = sitofp i64 %a to float 21 ret float %conv 22 } 23 24 ; Function Attrs: norecurse nounwind readnone uwtable 25 define dso_local double @int32_to_double(i32 %a) local_unnamed_addr #0 { 26 entry: 27 %conv = sitofp i32 %a to double 28 ret double %conv 29 } 30 31 ; Function Attrs: norecurse nounwind readnone uwtable 32 define dso_local double @int64_to_double(i64 %a) local_unnamed_addr #0 { 33 entry: 34 %conv = sitofp i64 %a to double 35 ret double %conv 36 } 37 38 attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } 39 40 !llvm.module.flags = !{!0} 41 !llvm.ident = !{!1} 42 43 !0 = !{i32 1, !"wchar_size", i32 4} 44 !1 = !{!"clang version 7.0.0"} 45 46... 47--- 48name: int32_to_float 49alignment: 16 50legalized: true 51regBankSelected: true 52tracksRegLiveness: true 53registers: 54 - { id: 0, class: gpr } 55 - { id: 1, class: vecr } 56 - { id: 2, class: vecr } 57body: | 58 bb.1.entry: 59 liveins: $edi 60 61 ; CHECK-LABEL: name: int32_to_float 62 ; CHECK: liveins: $edi 63 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 64 ; CHECK: %1:fr32 = nofpexcept CVTSI2SSrr [[COPY]], implicit $mxcsr 65 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1 66 ; CHECK: $xmm0 = COPY [[COPY1]] 67 ; CHECK: RET 0, implicit $xmm0 68 %0:gpr(s32) = COPY $edi 69 %1:vecr(s32) = G_SITOFP %0(s32) 70 %2:vecr(s128) = G_ANYEXT %1(s32) 71 $xmm0 = COPY %2(s128) 72 RET 0, implicit $xmm0 73 74... 75--- 76name: int64_to_float 77alignment: 16 78legalized: true 79regBankSelected: true 80tracksRegLiveness: true 81registers: 82 - { id: 0, class: gpr } 83 - { id: 1, class: vecr } 84 - { id: 2, class: vecr } 85body: | 86 bb.1.entry: 87 liveins: $rdi 88 89 ; CHECK-LABEL: name: int64_to_float 90 ; CHECK: liveins: $rdi 91 ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 92 ; CHECK: %1:fr32 = nofpexcept CVTSI642SSrr [[COPY]], implicit $mxcsr 93 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1 94 ; CHECK: $xmm0 = COPY [[COPY1]] 95 ; CHECK: RET 0, implicit $xmm0 96 %0:gpr(s64) = COPY $rdi 97 %1:vecr(s32) = G_SITOFP %0(s64) 98 %2:vecr(s128) = G_ANYEXT %1(s32) 99 $xmm0 = COPY %2(s128) 100 RET 0, implicit $xmm0 101 102... 103--- 104name: int32_to_double 105alignment: 16 106legalized: true 107regBankSelected: true 108tracksRegLiveness: true 109registers: 110 - { id: 0, class: gpr } 111 - { id: 1, class: vecr } 112 - { id: 2, class: vecr } 113body: | 114 bb.1.entry: 115 liveins: $edi 116 117 ; CHECK-LABEL: name: int32_to_double 118 ; CHECK: liveins: $edi 119 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 120 ; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]] 121 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SDrr]] 122 ; CHECK: $xmm0 = COPY [[COPY1]] 123 ; CHECK: RET 0, implicit $xmm0 124 %0:gpr(s32) = COPY $edi 125 %1:vecr(s64) = G_SITOFP %0(s32) 126 %2:vecr(s128) = G_ANYEXT %1(s64) 127 $xmm0 = COPY %2(s128) 128 RET 0, implicit $xmm0 129 130... 131--- 132name: int64_to_double 133alignment: 16 134legalized: true 135regBankSelected: true 136tracksRegLiveness: true 137registers: 138 - { id: 0, class: gpr } 139 - { id: 1, class: vecr } 140 - { id: 2, class: vecr } 141body: | 142 bb.1.entry: 143 liveins: $rdi 144 145 ; CHECK-LABEL: name: int64_to_double 146 ; CHECK: liveins: $rdi 147 ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 148 ; CHECK: %1:fr64 = nofpexcept CVTSI642SDrr [[COPY]], implicit $mxcsr 149 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1 150 ; CHECK: $xmm0 = COPY [[COPY1]] 151 ; CHECK: RET 0, implicit $xmm0 152 %0:gpr(s64) = COPY $rdi 153 %1:vecr(s64) = G_SITOFP %0(s64) 154 %2:vecr(s128) = G_ANYEXT %1(s64) 155 $xmm0 = COPY %2(s128) 156 RET 0, implicit $xmm0 157 158... 159