1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -mtriple=x86_64-linux-gnu -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - 2>&1 | FileCheck %s 3 4define i8 @zext_i1_to_i8(i1 %val) { 5 ; CHECK-LABEL: name: zext_i1_to_i8 6 ; CHECK: bb.1 (%ir-block.0): 7 ; CHECK: liveins: $edi 8 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 9 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 10 ; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1) 11 ; CHECK: $al = COPY [[ZEXT]](s8) 12 ; CHECK: RET 0, implicit $al 13 %res = zext i1 %val to i8 14 ret i8 %res 15} 16 17define i16 @zext_i1_to_i16(i1 %val) { 18 ; CHECK-LABEL: name: zext_i1_to_i16 19 ; CHECK: bb.1 (%ir-block.0): 20 ; CHECK: liveins: $edi 21 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 22 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 23 ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s1) 24 ; CHECK: $ax = COPY [[ZEXT]](s16) 25 ; CHECK: RET 0, implicit $ax 26 %res = zext i1 %val to i16 27 ret i16 %res 28} 29 30define i32 @zext_i1_to_i32(i1 %val) { 31 ; CHECK-LABEL: name: zext_i1_to_i32 32 ; CHECK: bb.1 (%ir-block.0): 33 ; CHECK: liveins: $edi 34 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 35 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 36 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1) 37 ; CHECK: $eax = COPY [[ZEXT]](s32) 38 ; CHECK: RET 0, implicit $eax 39 %res = zext i1 %val to i32 40 ret i32 %res 41} 42 43define i64 @zext_i1_to_i64(i1 %val) { 44 ; CHECK-LABEL: name: zext_i1_to_i64 45 ; CHECK: bb.1 (%ir-block.0): 46 ; CHECK: liveins: $edi 47 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 48 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) 49 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s1) 50 ; CHECK: $rax = COPY [[ZEXT]](s64) 51 ; CHECK: RET 0, implicit $rax 52 %res = zext i1 %val to i64 53 ret i64 %res 54} 55 56define i16 @zext_i8_to_i16(i8 %val) { 57 ; CHECK-LABEL: name: zext_i8_to_i16 58 ; CHECK: bb.1 (%ir-block.0): 59 ; CHECK: liveins: $edi 60 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 61 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 62 ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s8) 63 ; CHECK: $ax = COPY [[ZEXT]](s16) 64 ; CHECK: RET 0, implicit $ax 65 %res = zext i8 %val to i16 66 ret i16 %res 67} 68 69define i32 @zext_i8_to_i32(i8 %val) { 70 ; CHECK-LABEL: name: zext_i8_to_i32 71 ; CHECK: bb.1 (%ir-block.0): 72 ; CHECK: liveins: $edi 73 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 74 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 75 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8) 76 ; CHECK: $eax = COPY [[ZEXT]](s32) 77 ; CHECK: RET 0, implicit $eax 78 %res = zext i8 %val to i32 79 ret i32 %res 80} 81 82define i64 @zext_i8_to_i64(i8 %val) { 83 ; CHECK-LABEL: name: zext_i8_to_i64 84 ; CHECK: bb.1 (%ir-block.0): 85 ; CHECK: liveins: $edi 86 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 87 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 88 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8) 89 ; CHECK: $rax = COPY [[ZEXT]](s64) 90 ; CHECK: RET 0, implicit $rax 91 %res = zext i8 %val to i64 92 ret i64 %res 93} 94 95define i32 @zext_i16_to_i32(i16 %val) { 96 ; CHECK-LABEL: name: zext_i16_to_i32 97 ; CHECK: bb.1 (%ir-block.0): 98 ; CHECK: liveins: $edi 99 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 100 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 101 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16) 102 ; CHECK: $eax = COPY [[ZEXT]](s32) 103 ; CHECK: RET 0, implicit $eax 104 %res = zext i16 %val to i32 105 ret i32 %res 106} 107 108define i64 @zext_i16_to_i64(i16 %val) { 109 ; CHECK-LABEL: name: zext_i16_to_i64 110 ; CHECK: bb.1 (%ir-block.0): 111 ; CHECK: liveins: $edi 112 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 113 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 114 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s16) 115 ; CHECK: $rax = COPY [[ZEXT]](s64) 116 ; CHECK: RET 0, implicit $rax 117 %res = zext i16 %val to i64 118 ret i64 %res 119} 120 121define i64 @zext_i32_to_i64(i32 %val) { 122 ; CHECK-LABEL: name: zext_i32_to_i64 123 ; CHECK: bb.1 (%ir-block.0): 124 ; CHECK: liveins: $edi 125 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 126 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) 127 ; CHECK: $rax = COPY [[ZEXT]](s64) 128 ; CHECK: RET 0, implicit $rax 129 %res = zext i32 %val to i64 130 ret i64 %res 131} 132 133define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) { 134 ; CHECK-LABEL: name: test_sdiv_i8 135 ; CHECK: bb.1 (%ir-block.0): 136 ; CHECK: liveins: $edi, $esi 137 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 138 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 139 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 140 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 141 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]] 142 ; CHECK: $al = COPY [[SDIV]](s8) 143 ; CHECK: RET 0, implicit $al 144 %res = sdiv i8 %arg1, %arg2 145 ret i8 %res 146} 147 148define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) { 149 ; CHECK-LABEL: name: test_sdiv_i16 150 ; CHECK: bb.1 (%ir-block.0): 151 ; CHECK: liveins: $edi, $esi 152 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 153 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 154 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 155 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 156 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]] 157 ; CHECK: $ax = COPY [[SDIV]](s16) 158 ; CHECK: RET 0, implicit $ax 159 %res = sdiv i16 %arg1, %arg2 160 ret i16 %res 161} 162 163define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) { 164 ; CHECK-LABEL: name: test_sdiv_i32 165 ; CHECK: bb.1 (%ir-block.0): 166 ; CHECK: liveins: $edi, $esi 167 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 168 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 169 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]] 170 ; CHECK: $eax = COPY [[SDIV]](s32) 171 ; CHECK: RET 0, implicit $eax 172 %res = sdiv i32 %arg1, %arg2 173 ret i32 %res 174} 175 176define i64 @test_sdiv_i64(i64 %arg1, i64 %arg2) { 177 ; CHECK-LABEL: name: test_sdiv_i64 178 ; CHECK: bb.1 (%ir-block.0): 179 ; CHECK: liveins: $rdi, $rsi 180 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 181 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 182 ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]] 183 ; CHECK: $rax = COPY [[SDIV]](s64) 184 ; CHECK: RET 0, implicit $rax 185 %res = sdiv i64 %arg1, %arg2 186 ret i64 %res 187} 188define float @test_fptrunc(double %in) { 189 ; CHECK-LABEL: name: test_fptrunc 190 ; CHECK: bb.1 (%ir-block.0): 191 ; CHECK: liveins: $xmm0 192 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $xmm0 193 ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64) 194 ; CHECK: $xmm0 = COPY [[FPTRUNC]](s32) 195 ; CHECK: RET 0, implicit $xmm0 196 %res = fptrunc double %in to float 197 ret float %res 198} 199 200define i8 @test_srem_i8(i8 %arg1, i8 %arg2) { 201 ; CHECK-LABEL: name: test_srem_i8 202 ; CHECK: bb.1 (%ir-block.0): 203 ; CHECK: liveins: $edi, $esi 204 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 205 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 206 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 207 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 208 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]] 209 ; CHECK: $al = COPY [[SREM]](s8) 210 ; CHECK: RET 0, implicit $al 211 %res = srem i8 %arg1, %arg2 212 ret i8 %res 213} 214 215define i16 @test_srem_i16(i16 %arg1, i16 %arg2) { 216 ; CHECK-LABEL: name: test_srem_i16 217 ; CHECK: bb.1 (%ir-block.0): 218 ; CHECK: liveins: $edi, $esi 219 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 220 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 221 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 222 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 223 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]] 224 ; CHECK: $ax = COPY [[SREM]](s16) 225 ; CHECK: RET 0, implicit $ax 226 %res = srem i16 %arg1, %arg2 227 ret i16 %res 228} 229 230define i32 @test_srem_i32(i32 %arg1, i32 %arg2) { 231 ; CHECK-LABEL: name: test_srem_i32 232 ; CHECK: bb.1 (%ir-block.0): 233 ; CHECK: liveins: $edi, $esi 234 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 235 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 236 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]] 237 ; CHECK: $eax = COPY [[SREM]](s32) 238 ; CHECK: RET 0, implicit $eax 239 %res = srem i32 %arg1, %arg2 240 ret i32 %res 241} 242 243define i64 @test_srem_i64(i64 %arg1, i64 %arg2) { 244 ; CHECK-LABEL: name: test_srem_i64 245 ; CHECK: bb.1 (%ir-block.0): 246 ; CHECK: liveins: $rdi, $rsi 247 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 248 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 249 ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]] 250 ; CHECK: $rax = COPY [[SREM]](s64) 251 ; CHECK: RET 0, implicit $rax 252 %res = srem i64 %arg1, %arg2 253 ret i64 %res 254} 255 256define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) { 257 ; CHECK-LABEL: name: test_udiv_i8 258 ; CHECK: bb.1 (%ir-block.0): 259 ; CHECK: liveins: $edi, $esi 260 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 261 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 262 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 263 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 264 ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]] 265 ; CHECK: $al = COPY [[UDIV]](s8) 266 ; CHECK: RET 0, implicit $al 267 %res = udiv i8 %arg1, %arg2 268 ret i8 %res 269} 270 271define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) { 272 ; CHECK-LABEL: name: test_udiv_i16 273 ; CHECK: bb.1 (%ir-block.0): 274 ; CHECK: liveins: $edi, $esi 275 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 276 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 277 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 278 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 279 ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]] 280 ; CHECK: $ax = COPY [[UDIV]](s16) 281 ; CHECK: RET 0, implicit $ax 282 %res = udiv i16 %arg1, %arg2 283 ret i16 %res 284} 285 286define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) { 287 ; CHECK-LABEL: name: test_udiv_i32 288 ; CHECK: bb.1 (%ir-block.0): 289 ; CHECK: liveins: $edi, $esi 290 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 291 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 292 ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]] 293 ; CHECK: $eax = COPY [[UDIV]](s32) 294 ; CHECK: RET 0, implicit $eax 295 %res = udiv i32 %arg1, %arg2 296 ret i32 %res 297} 298 299define i64 @test_udiv_i64(i64 %arg1, i64 %arg2) { 300 ; CHECK-LABEL: name: test_udiv_i64 301 ; CHECK: bb.1 (%ir-block.0): 302 ; CHECK: liveins: $rdi, $rsi 303 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 304 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 305 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]] 306 ; CHECK: $rax = COPY [[UDIV]](s64) 307 ; CHECK: RET 0, implicit $rax 308 %res = udiv i64 %arg1, %arg2 309 ret i64 %res 310} 311 312define i8 @test_urem_i8(i8 %arg1, i8 %arg2) { 313 ; CHECK-LABEL: name: test_urem_i8 314 ; CHECK: bb.1 (%ir-block.0): 315 ; CHECK: liveins: $edi, $esi 316 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 317 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 318 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 319 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 320 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]] 321 ; CHECK: $al = COPY [[UREM]](s8) 322 ; CHECK: RET 0, implicit $al 323 %res = urem i8 %arg1, %arg2 324 ret i8 %res 325} 326 327define i16 @test_urem_i16(i16 %arg1, i16 %arg2) { 328 ; CHECK-LABEL: name: test_urem_i16 329 ; CHECK: bb.1 (%ir-block.0): 330 ; CHECK: liveins: $edi, $esi 331 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 332 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 333 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 334 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 335 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]] 336 ; CHECK: $ax = COPY [[UREM]](s16) 337 ; CHECK: RET 0, implicit $ax 338 %res = urem i16 %arg1, %arg2 339 ret i16 %res 340} 341 342define i32 @test_urem_i32(i32 %arg1, i32 %arg2) { 343 ; CHECK-LABEL: name: test_urem_i32 344 ; CHECK: bb.1 (%ir-block.0): 345 ; CHECK: liveins: $edi, $esi 346 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 347 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 348 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]] 349 ; CHECK: $eax = COPY [[UREM]](s32) 350 ; CHECK: RET 0, implicit $eax 351 %res = urem i32 %arg1, %arg2 352 ret i32 %res 353} 354 355define i64 @test_urem_i64(i64 %arg1, i64 %arg2) { 356 ; CHECK-LABEL: name: test_urem_i64 357 ; CHECK: bb.1 (%ir-block.0): 358 ; CHECK: liveins: $rdi, $rsi 359 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 360 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 361 ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]] 362 ; CHECK: $rax = COPY [[UREM]](s64) 363 ; CHECK: RET 0, implicit $rax 364 %res = urem i64 %arg1, %arg2 365 ret i64 %res 366} 367 368define <2 x float> @test_const_v2f32() { 369 ; CHECK-LABEL: name: test_const_v2f32 370 ; CHECK: bb.1 (%ir-block.0): 371 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 372 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32) 373 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>) 374 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF 375 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[DEF]](s32), [[DEF]](s32) 376 ; CHECK-NEXT: $xmm0 = COPY [[BUILD_VECTOR1]](<4 x s32>) 377 ; CHECK-NEXT: RET 0, implicit $xmm0 378 ret <2 x float> <float 1.0, float 1.0> 379} 380 381define <3 x float> @test_const_v3f32() { 382 ; CHECK-LABEL: name: test_const_v3f32 383 ; CHECK: bb.1 (%ir-block.0): 384 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 385 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32) 386 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>) 387 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF 388 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[DEF]](s32) 389 ; CHECK-NEXT: $xmm0 = COPY [[BUILD_VECTOR1]](<4 x s32>) 390 ; CHECK-NEXT: RET 0, implicit $xmm0 391 ret <3 x float> <float 1.0, float 1.0, float 1.0> 392} 393 394define <5 x float> @test_const_v5f32() { 395 ; CHECK-LABEL: name: test_const_v5f32 396 ; CHECK: bb.1 (%ir-block.0): 397 ; CHECK-NEXT: liveins: $rdi 398 ; CHECK-NEXT: {{ $}} 399 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi 400 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 401 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) 402 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<5 x s32>), [[COPY]](p0) :: (store (<5 x s32>), align 32) 403 ; CHECK-NEXT: $rax = COPY [[COPY]](p0) 404 ; CHECK-NEXT: RET 0 405 ret <5 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0> 406} 407 408define <6 x float> @test_const_v6f32() { 409 ; CHECK-LABEL: name: test_const_v6f32 410 ; CHECK: bb.1 (%ir-block.0): 411 ; CHECK-NEXT: liveins: $rdi 412 ; CHECK-NEXT: {{ $}} 413 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi 414 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 415 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) 416 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<6 x s32>), [[COPY]](p0) :: (store (<6 x s32>), align 32) 417 ; CHECK-NEXT: $rax = COPY [[COPY]](p0) 418 ; CHECK-NEXT: RET 0 419 ret <6 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0> 420} 421