1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL 3 4--- | 5 define <64 x i8> @test_sub_v64i8(<64 x i8> %arg1, <64 x i8> %arg2) #0 { 6 %ret = sub <64 x i8> %arg1, %arg2 7 ret <64 x i8> %ret 8 } 9 10 define <32 x i16> @test_sub_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) #0 { 11 %ret = sub <32 x i16> %arg1, %arg2 12 ret <32 x i16> %ret 13 } 14 15 define <16 x i32> @test_sub_v16i32(<16 x i32> %arg1, <16 x i32> %arg2) #1 { 16 %ret = sub <16 x i32> %arg1, %arg2 17 ret <16 x i32> %ret 18 } 19 20 define <8 x i64> @test_sub_v8i64(<8 x i64> %arg1, <8 x i64> %arg2) #1 { 21 %ret = sub <8 x i64> %arg1, %arg2 22 ret <8 x i64> %ret 23 } 24 25 attributes #0 = { "target-features"="+avx512f,+avx512bw" } 26 attributes #1 = { "target-features"="+avx512f" } 27... 28--- 29name: test_sub_v64i8 30alignment: 16 31legalized: true 32regBankSelected: true 33registers: 34 - { id: 0, class: vecr } 35 - { id: 1, class: vecr } 36 - { id: 2, class: vecr } 37body: | 38 bb.1 (%ir-block.0): 39 liveins: $zmm0, $zmm1 40 41 ; ALL-LABEL: name: test_sub_v64i8 42 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 43 ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1 44 ; ALL: [[VPSUBBZrr:%[0-9]+]]:vr512 = VPSUBBZrr [[COPY]], [[COPY1]] 45 ; ALL: $zmm0 = COPY [[VPSUBBZrr]] 46 ; ALL: RET 0, implicit $zmm0 47 %0(<64 x s8>) = COPY $zmm0 48 %1(<64 x s8>) = COPY $zmm1 49 %2(<64 x s8>) = G_SUB %0, %1 50 $zmm0 = COPY %2(<64 x s8>) 51 RET 0, implicit $zmm0 52 53... 54--- 55name: test_sub_v32i16 56alignment: 16 57legalized: true 58regBankSelected: true 59registers: 60 - { id: 0, class: vecr } 61 - { id: 1, class: vecr } 62 - { id: 2, class: vecr } 63body: | 64 bb.1 (%ir-block.0): 65 liveins: $zmm0, $zmm1 66 67 ; ALL-LABEL: name: test_sub_v32i16 68 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 69 ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1 70 ; ALL: [[VPSUBWZrr:%[0-9]+]]:vr512 = VPSUBWZrr [[COPY]], [[COPY1]] 71 ; ALL: $zmm0 = COPY [[VPSUBWZrr]] 72 ; ALL: RET 0, implicit $zmm0 73 %0(<32 x s16>) = COPY $zmm0 74 %1(<32 x s16>) = COPY $zmm1 75 %2(<32 x s16>) = G_SUB %0, %1 76 $zmm0 = COPY %2(<32 x s16>) 77 RET 0, implicit $zmm0 78 79... 80--- 81name: test_sub_v16i32 82alignment: 16 83legalized: true 84regBankSelected: true 85registers: 86 - { id: 0, class: vecr } 87 - { id: 1, class: vecr } 88 - { id: 2, class: vecr } 89body: | 90 bb.1 (%ir-block.0): 91 liveins: $zmm0, $zmm1 92 93 ; ALL-LABEL: name: test_sub_v16i32 94 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 95 ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1 96 ; ALL: [[VPSUBDZrr:%[0-9]+]]:vr512 = VPSUBDZrr [[COPY]], [[COPY1]] 97 ; ALL: $zmm0 = COPY [[VPSUBDZrr]] 98 ; ALL: RET 0, implicit $zmm0 99 %0(<16 x s32>) = COPY $zmm0 100 %1(<16 x s32>) = COPY $zmm1 101 %2(<16 x s32>) = G_SUB %0, %1 102 $zmm0 = COPY %2(<16 x s32>) 103 RET 0, implicit $zmm0 104 105... 106--- 107name: test_sub_v8i64 108alignment: 16 109legalized: true 110regBankSelected: true 111registers: 112 - { id: 0, class: vecr } 113 - { id: 1, class: vecr } 114 - { id: 2, class: vecr } 115body: | 116 bb.1 (%ir-block.0): 117 liveins: $zmm0, $zmm1 118 119 ; ALL-LABEL: name: test_sub_v8i64 120 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 121 ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1 122 ; ALL: [[VPSUBQZrr:%[0-9]+]]:vr512 = VPSUBQZrr [[COPY]], [[COPY1]] 123 ; ALL: $zmm0 = COPY [[VPSUBQZrr]] 124 ; ALL: RET 0, implicit $zmm0 125 %0(<8 x s64>) = COPY $zmm0 126 %1(<8 x s64>) = COPY $zmm1 127 %2(<8 x s64>) = G_SUB %0, %1 128 $zmm0 = COPY %2(<8 x s64>) 129 RET 0, implicit $zmm0 130 131... 132