1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL 3 4--- | 5 define i16 @test_mul_i16(i16 %arg1, i16 %arg2) { 6 %ret = mul i16 %arg1, %arg2 7 ret i16 %ret 8 } 9 10 define i32 @test_mul_i32(i32 %arg1, i32 %arg2) { 11 %ret = mul i32 %arg1, %arg2 12 ret i32 %ret 13 } 14 15 define i64 @test_mul_i64(i64 %arg1, i64 %arg2) { 16 %ret = mul i64 %arg1, %arg2 17 ret i64 %ret 18 } 19 20... 21--- 22name: test_mul_i16 23alignment: 16 24legalized: true 25regBankSelected: true 26registers: 27 - { id: 0, class: gpr } 28 - { id: 1, class: gpr } 29 - { id: 2, class: gpr } 30body: | 31 bb.1 (%ir-block.0): 32 liveins: $edi, $esi 33 34 ; ALL-LABEL: name: test_mul_i16 35 ; ALL: liveins: $edi, $esi 36 ; ALL-NEXT: {{ $}} 37 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di 38 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si 39 ; ALL-NEXT: [[IMUL16rr:%[0-9]+]]:gr16 = IMUL16rr [[COPY]], [[COPY1]], implicit-def dead $eflags 40 ; ALL-NEXT: $ax = COPY [[IMUL16rr]] 41 ; ALL-NEXT: RET 0, implicit $ax 42 %0(s16) = COPY $di 43 %1(s16) = COPY $si 44 %2(s16) = G_MUL %0, %1 45 $ax = COPY %2(s16) 46 RET 0, implicit $ax 47 48... 49--- 50name: test_mul_i32 51alignment: 16 52legalized: true 53regBankSelected: true 54registers: 55 - { id: 0, class: gpr } 56 - { id: 1, class: gpr } 57 - { id: 2, class: gpr } 58body: | 59 bb.1 (%ir-block.0): 60 liveins: $edi, $esi 61 62 ; ALL-LABEL: name: test_mul_i32 63 ; ALL: liveins: $edi, $esi 64 ; ALL-NEXT: {{ $}} 65 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 66 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 67 ; ALL-NEXT: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[COPY]], [[COPY1]], implicit-def dead $eflags 68 ; ALL-NEXT: $eax = COPY [[IMUL32rr]] 69 ; ALL-NEXT: RET 0, implicit $eax 70 %0(s32) = COPY $edi 71 %1(s32) = COPY $esi 72 %2(s32) = G_MUL %0, %1 73 $eax = COPY %2(s32) 74 RET 0, implicit $eax 75 76... 77--- 78name: test_mul_i64 79alignment: 16 80legalized: true 81regBankSelected: true 82registers: 83 - { id: 0, class: gpr } 84 - { id: 1, class: gpr } 85 - { id: 2, class: gpr } 86body: | 87 bb.1 (%ir-block.0): 88 liveins: $rdi, $rsi 89 90 ; ALL-LABEL: name: test_mul_i64 91 ; ALL: liveins: $rdi, $rsi 92 ; ALL-NEXT: {{ $}} 93 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 94 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi 95 ; ALL-NEXT: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[COPY]], [[COPY1]], implicit-def dead $eflags 96 ; ALL-NEXT: $rax = COPY [[IMUL64rr]] 97 ; ALL-NEXT: RET 0, implicit $rax 98 %0(s64) = COPY $rdi 99 %1(s64) = COPY $rsi 100 %2(s64) = G_MUL %0, %1 101 $rax = COPY %2(s64) 102 RET 0, implicit $rax 103 104... 105