1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK 3 4--- | 5 define i32 @test_icmp_eq_i8(i8 %a, i8 %b) { 6 %r = icmp eq i8 %a, %b 7 %res = zext i1 %r to i32 8 ret i32 %res 9 } 10 11 define i32 @test_icmp_eq_i16(i16 %a, i16 %b) { 12 %r = icmp eq i16 %a, %b 13 %res = zext i1 %r to i32 14 ret i32 %res 15 } 16 17 define i32 @test_icmp_eq_i64(i64 %a, i64 %b) { 18 %r = icmp eq i64 %a, %b 19 %res = zext i1 %r to i32 20 ret i32 %res 21 } 22 23 define i32 @test_icmp_eq_i32(i32 %a, i32 %b) { 24 %r = icmp eq i32 %a, %b 25 %res = zext i1 %r to i32 26 ret i32 %res 27 } 28 29 define i32 @test_icmp_ne_i32(i32 %a, i32 %b) { 30 %r = icmp ne i32 %a, %b 31 %res = zext i1 %r to i32 32 ret i32 %res 33 } 34 35 define i32 @test_icmp_ugt_i32(i32 %a, i32 %b) { 36 %r = icmp ugt i32 %a, %b 37 %res = zext i1 %r to i32 38 ret i32 %res 39 } 40 41 define i32 @test_icmp_uge_i32(i32 %a, i32 %b) { 42 %r = icmp uge i32 %a, %b 43 %res = zext i1 %r to i32 44 ret i32 %res 45 } 46 47 define i32 @test_icmp_ult_i32(i32 %a, i32 %b) { 48 %r = icmp ult i32 %a, %b 49 %res = zext i1 %r to i32 50 ret i32 %res 51 } 52 53 define i32 @test_icmp_ule_i32(i32 %a, i32 %b) { 54 %r = icmp ule i32 %a, %b 55 %res = zext i1 %r to i32 56 ret i32 %res 57 } 58 59 define i32 @test_icmp_sgt_i32(i32 %a, i32 %b) { 60 %r = icmp sgt i32 %a, %b 61 %res = zext i1 %r to i32 62 ret i32 %res 63 } 64 65 define i32 @test_icmp_sge_i32(i32 %a, i32 %b) { 66 %r = icmp sge i32 %a, %b 67 %res = zext i1 %r to i32 68 ret i32 %res 69 } 70 71 define i32 @test_icmp_slt_i32(i32 %a, i32 %b) { 72 %r = icmp slt i32 %a, %b 73 %res = zext i1 %r to i32 74 ret i32 %res 75 } 76 77 define i32 @test_icmp_sle_i32(i32 %a, i32 %b) { 78 %r = icmp sle i32 %a, %b 79 %res = zext i1 %r to i32 80 ret i32 %res 81 } 82 83... 84--- 85name: test_icmp_eq_i8 86alignment: 16 87legalized: true 88regBankSelected: true 89registers: 90 - { id: 0, class: gpr } 91 - { id: 1, class: gpr } 92 - { id: 2, class: _ } 93 - { id: 3, class: gpr } 94 - { id: 4, class: gpr } 95 - { id: 5, class: gpr } 96 - { id: 6, class: gpr } 97body: | 98 bb.1 (%ir-block.0): 99 liveins: $edi, $esi 100 101 ; CHECK-LABEL: name: test_icmp_eq_i8 102 ; CHECK: liveins: $edi, $esi 103 ; CHECK-NEXT: {{ $}} 104 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil 105 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY $sil 106 ; CHECK-NEXT: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags 107 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags 108 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 109 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 110 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 111 ; CHECK-NEXT: RET 0, implicit $eax 112 %0(s8) = COPY $dil 113 %1(s8) = COPY $sil 114 %4(s8) = G_ICMP intpred(eq), %0(s8), %1 115 %5(s32) = G_CONSTANT i32 1 116 %6(s32) = G_ANYEXT %4(s8) 117 %3(s32) = G_AND %6, %5 118 $eax = COPY %3(s32) 119 RET 0, implicit $eax 120 121... 122--- 123name: test_icmp_eq_i16 124alignment: 16 125legalized: true 126regBankSelected: true 127registers: 128 - { id: 0, class: gpr } 129 - { id: 1, class: gpr } 130 - { id: 2, class: _ } 131 - { id: 3, class: gpr } 132 - { id: 4, class: gpr } 133 - { id: 5, class: gpr } 134 - { id: 6, class: gpr } 135body: | 136 bb.1 (%ir-block.0): 137 liveins: $edi, $esi 138 139 ; CHECK-LABEL: name: test_icmp_eq_i16 140 ; CHECK: liveins: $edi, $esi 141 ; CHECK-NEXT: {{ $}} 142 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di 143 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si 144 ; CHECK-NEXT: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags 145 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags 146 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 147 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 148 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 149 ; CHECK-NEXT: RET 0, implicit $eax 150 %0(s16) = COPY $di 151 %1(s16) = COPY $si 152 %4(s8) = G_ICMP intpred(eq), %0(s16), %1 153 %5(s32) = G_CONSTANT i32 1 154 %6(s32) = G_ANYEXT %4(s8) 155 %3(s32) = G_AND %6, %5 156 $eax = COPY %3(s32) 157 RET 0, implicit $eax 158 159... 160--- 161name: test_icmp_eq_i64 162alignment: 16 163legalized: true 164regBankSelected: true 165registers: 166 - { id: 0, class: gpr } 167 - { id: 1, class: gpr } 168 - { id: 2, class: _ } 169 - { id: 3, class: gpr } 170 - { id: 4, class: gpr } 171 - { id: 5, class: gpr } 172 - { id: 6, class: gpr } 173body: | 174 bb.1 (%ir-block.0): 175 liveins: $rdi, $rsi 176 177 ; CHECK-LABEL: name: test_icmp_eq_i64 178 ; CHECK: liveins: $rdi, $rsi 179 ; CHECK-NEXT: {{ $}} 180 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 181 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi 182 ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags 183 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags 184 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 185 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 186 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 187 ; CHECK-NEXT: RET 0, implicit $eax 188 %0(s64) = COPY $rdi 189 %1(s64) = COPY $rsi 190 %4(s8) = G_ICMP intpred(eq), %0(s64), %1 191 %5(s32) = G_CONSTANT i32 1 192 %6(s32) = G_ANYEXT %4(s8) 193 %3(s32) = G_AND %6, %5 194 $eax = COPY %3(s32) 195 RET 0, implicit $eax 196 197... 198--- 199name: test_icmp_eq_i32 200alignment: 16 201legalized: true 202regBankSelected: true 203registers: 204 - { id: 0, class: gpr } 205 - { id: 1, class: gpr } 206 - { id: 2, class: _ } 207 - { id: 3, class: gpr } 208 - { id: 4, class: gpr } 209 - { id: 5, class: gpr } 210 - { id: 6, class: gpr } 211body: | 212 bb.1 (%ir-block.0): 213 liveins: $edi, $esi 214 215 ; CHECK-LABEL: name: test_icmp_eq_i32 216 ; CHECK: liveins: $edi, $esi 217 ; CHECK-NEXT: {{ $}} 218 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 219 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 220 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 221 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags 222 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 223 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 224 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 225 ; CHECK-NEXT: RET 0, implicit $eax 226 %0(s32) = COPY $edi 227 %1(s32) = COPY $esi 228 %4(s8) = G_ICMP intpred(eq), %0(s32), %1 229 %5(s32) = G_CONSTANT i32 1 230 %6(s32) = G_ANYEXT %4(s8) 231 %3(s32) = G_AND %6, %5 232 $eax = COPY %3(s32) 233 RET 0, implicit $eax 234 235... 236--- 237name: test_icmp_ne_i32 238alignment: 16 239legalized: true 240regBankSelected: true 241registers: 242 - { id: 0, class: gpr } 243 - { id: 1, class: gpr } 244 - { id: 2, class: _ } 245 - { id: 3, class: gpr } 246 - { id: 4, class: gpr } 247 - { id: 5, class: gpr } 248 - { id: 6, class: gpr } 249body: | 250 bb.1 (%ir-block.0): 251 liveins: $edi, $esi 252 253 ; CHECK-LABEL: name: test_icmp_ne_i32 254 ; CHECK: liveins: $edi, $esi 255 ; CHECK-NEXT: {{ $}} 256 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 257 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 258 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 259 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags 260 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 261 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 262 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 263 ; CHECK-NEXT: RET 0, implicit $eax 264 %0(s32) = COPY $edi 265 %1(s32) = COPY $esi 266 %4(s8) = G_ICMP intpred(ne), %0(s32), %1 267 %5(s32) = G_CONSTANT i32 1 268 %6(s32) = G_ANYEXT %4(s8) 269 %3(s32) = G_AND %6, %5 270 $eax = COPY %3(s32) 271 RET 0, implicit $eax 272 273... 274--- 275name: test_icmp_ugt_i32 276alignment: 16 277legalized: true 278regBankSelected: true 279registers: 280 - { id: 0, class: gpr } 281 - { id: 1, class: gpr } 282 - { id: 2, class: _ } 283 - { id: 3, class: gpr } 284 - { id: 4, class: gpr } 285 - { id: 5, class: gpr } 286 - { id: 6, class: gpr } 287body: | 288 bb.1 (%ir-block.0): 289 liveins: $edi, $esi 290 291 ; CHECK-LABEL: name: test_icmp_ugt_i32 292 ; CHECK: liveins: $edi, $esi 293 ; CHECK-NEXT: {{ $}} 294 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 295 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 296 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 297 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags 298 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 299 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 300 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 301 ; CHECK-NEXT: RET 0, implicit $eax 302 %0(s32) = COPY $edi 303 %1(s32) = COPY $esi 304 %4(s8) = G_ICMP intpred(ugt), %0(s32), %1 305 %5(s32) = G_CONSTANT i32 1 306 %6(s32) = G_ANYEXT %4(s8) 307 %3(s32) = G_AND %6, %5 308 $eax = COPY %3(s32) 309 RET 0, implicit $eax 310 311... 312--- 313name: test_icmp_uge_i32 314alignment: 16 315legalized: true 316regBankSelected: true 317registers: 318 - { id: 0, class: gpr } 319 - { id: 1, class: gpr } 320 - { id: 2, class: _ } 321 - { id: 3, class: gpr } 322 - { id: 4, class: gpr } 323 - { id: 5, class: gpr } 324 - { id: 6, class: gpr } 325body: | 326 bb.1 (%ir-block.0): 327 liveins: $edi, $esi 328 329 ; CHECK-LABEL: name: test_icmp_uge_i32 330 ; CHECK: liveins: $edi, $esi 331 ; CHECK-NEXT: {{ $}} 332 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 333 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 334 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 335 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags 336 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 337 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 338 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 339 ; CHECK-NEXT: RET 0, implicit $eax 340 %0(s32) = COPY $edi 341 %1(s32) = COPY $esi 342 %4(s8) = G_ICMP intpred(uge), %0(s32), %1 343 %5(s32) = G_CONSTANT i32 1 344 %6(s32) = G_ANYEXT %4(s8) 345 %3(s32) = G_AND %6, %5 346 $eax = COPY %3(s32) 347 RET 0, implicit $eax 348 349... 350--- 351name: test_icmp_ult_i32 352alignment: 16 353legalized: true 354regBankSelected: true 355registers: 356 - { id: 0, class: gpr } 357 - { id: 1, class: gpr } 358 - { id: 2, class: _ } 359 - { id: 3, class: gpr } 360 - { id: 4, class: gpr } 361 - { id: 5, class: gpr } 362 - { id: 6, class: gpr } 363body: | 364 bb.1 (%ir-block.0): 365 liveins: $edi, $esi 366 367 ; CHECK-LABEL: name: test_icmp_ult_i32 368 ; CHECK: liveins: $edi, $esi 369 ; CHECK-NEXT: {{ $}} 370 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 371 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 372 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 373 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags 374 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 375 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 376 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 377 ; CHECK-NEXT: RET 0, implicit $eax 378 %0(s32) = COPY $edi 379 %1(s32) = COPY $esi 380 %4(s8) = G_ICMP intpred(ult), %0(s32), %1 381 %5(s32) = G_CONSTANT i32 1 382 %6(s32) = G_ANYEXT %4(s8) 383 %3(s32) = G_AND %6, %5 384 $eax = COPY %3(s32) 385 RET 0, implicit $eax 386 387... 388--- 389name: test_icmp_ule_i32 390alignment: 16 391legalized: true 392regBankSelected: true 393registers: 394 - { id: 0, class: gpr } 395 - { id: 1, class: gpr } 396 - { id: 2, class: _ } 397 - { id: 3, class: gpr } 398 - { id: 4, class: gpr } 399 - { id: 5, class: gpr } 400 - { id: 6, class: gpr } 401body: | 402 bb.1 (%ir-block.0): 403 liveins: $edi, $esi 404 405 ; CHECK-LABEL: name: test_icmp_ule_i32 406 ; CHECK: liveins: $edi, $esi 407 ; CHECK-NEXT: {{ $}} 408 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 409 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 410 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 411 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags 412 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 413 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 414 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 415 ; CHECK-NEXT: RET 0, implicit $eax 416 %0(s32) = COPY $edi 417 %1(s32) = COPY $esi 418 %4(s8) = G_ICMP intpred(ule), %0(s32), %1 419 %5(s32) = G_CONSTANT i32 1 420 %6(s32) = G_ANYEXT %4(s8) 421 %3(s32) = G_AND %6, %5 422 $eax = COPY %3(s32) 423 RET 0, implicit $eax 424 425... 426--- 427name: test_icmp_sgt_i32 428alignment: 16 429legalized: true 430regBankSelected: true 431registers: 432 - { id: 0, class: gpr } 433 - { id: 1, class: gpr } 434 - { id: 2, class: _ } 435 - { id: 3, class: gpr } 436 - { id: 4, class: gpr } 437 - { id: 5, class: gpr } 438 - { id: 6, class: gpr } 439body: | 440 bb.1 (%ir-block.0): 441 liveins: $edi, $esi 442 443 ; CHECK-LABEL: name: test_icmp_sgt_i32 444 ; CHECK: liveins: $edi, $esi 445 ; CHECK-NEXT: {{ $}} 446 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 447 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 448 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 449 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags 450 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 451 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 452 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 453 ; CHECK-NEXT: RET 0, implicit $eax 454 %0(s32) = COPY $edi 455 %1(s32) = COPY $esi 456 %4(s8) = G_ICMP intpred(sgt), %0(s32), %1 457 %5(s32) = G_CONSTANT i32 1 458 %6(s32) = G_ANYEXT %4(s8) 459 %3(s32) = G_AND %6, %5 460 $eax = COPY %3(s32) 461 RET 0, implicit $eax 462 463... 464--- 465name: test_icmp_sge_i32 466alignment: 16 467legalized: true 468regBankSelected: true 469registers: 470 - { id: 0, class: gpr } 471 - { id: 1, class: gpr } 472 - { id: 2, class: _ } 473 - { id: 3, class: gpr } 474 - { id: 4, class: gpr } 475 - { id: 5, class: gpr } 476 - { id: 6, class: gpr } 477body: | 478 bb.1 (%ir-block.0): 479 liveins: $edi, $esi 480 481 ; CHECK-LABEL: name: test_icmp_sge_i32 482 ; CHECK: liveins: $edi, $esi 483 ; CHECK-NEXT: {{ $}} 484 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 485 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 486 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 487 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags 488 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 489 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 490 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 491 ; CHECK-NEXT: RET 0, implicit $eax 492 %0(s32) = COPY $edi 493 %1(s32) = COPY $esi 494 %4(s8) = G_ICMP intpred(sge), %0(s32), %1 495 %5(s32) = G_CONSTANT i32 1 496 %6(s32) = G_ANYEXT %4(s8) 497 %3(s32) = G_AND %6, %5 498 $eax = COPY %3(s32) 499 RET 0, implicit $eax 500 501... 502--- 503name: test_icmp_slt_i32 504alignment: 16 505legalized: true 506regBankSelected: true 507registers: 508 - { id: 0, class: gpr } 509 - { id: 1, class: gpr } 510 - { id: 2, class: _ } 511 - { id: 3, class: gpr } 512 - { id: 4, class: gpr } 513 - { id: 5, class: gpr } 514 - { id: 6, class: gpr } 515body: | 516 bb.1 (%ir-block.0): 517 liveins: $edi, $esi 518 519 ; CHECK-LABEL: name: test_icmp_slt_i32 520 ; CHECK: liveins: $edi, $esi 521 ; CHECK-NEXT: {{ $}} 522 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 523 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 524 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 525 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags 526 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 527 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 528 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 529 ; CHECK-NEXT: RET 0, implicit $eax 530 %0(s32) = COPY $edi 531 %1(s32) = COPY $esi 532 %4(s8) = G_ICMP intpred(slt), %0(s32), %1 533 %5(s32) = G_CONSTANT i32 1 534 %6(s32) = G_ANYEXT %4(s8) 535 %3(s32) = G_AND %6, %5 536 $eax = COPY %3(s32) 537 RET 0, implicit $eax 538 539... 540--- 541name: test_icmp_sle_i32 542alignment: 16 543legalized: true 544regBankSelected: true 545registers: 546 - { id: 0, class: gpr } 547 - { id: 1, class: gpr } 548 - { id: 2, class: _ } 549 - { id: 3, class: gpr } 550 - { id: 4, class: gpr } 551 - { id: 5, class: gpr } 552 - { id: 6, class: gpr } 553body: | 554 bb.1 (%ir-block.0): 555 liveins: $edi, $esi 556 557 ; CHECK-LABEL: name: test_icmp_sle_i32 558 ; CHECK: liveins: $edi, $esi 559 ; CHECK-NEXT: {{ $}} 560 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 561 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 562 ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 563 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags 564 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 565 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags 566 ; CHECK-NEXT: $eax = COPY [[AND32ri]] 567 ; CHECK-NEXT: RET 0, implicit $eax 568 %0(s32) = COPY $edi 569 %1(s32) = COPY $esi 570 %4(s8) = G_ICMP intpred(sle), %0(s32), %1 571 %5(s32) = G_CONSTANT i32 1 572 %6(s32) = G_ANYEXT %4(s8) 573 %3(s32) = G_AND %6, %5 574 $eax = COPY %3(s32) 575 RET 0, implicit $eax 576 577... 578