1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL 3 4--- | 5 define i8 @test_and_i8(i8 %arg1, i8 %arg2) { 6 %ret = and i8 %arg1, %arg2 7 ret i8 %ret 8 } 9 10 define i16 @test_and_i16(i16 %arg1, i16 %arg2) { 11 %ret = and i16 %arg1, %arg2 12 ret i16 %ret 13 } 14 15 define i32 @test_and_i32(i32 %arg1, i32 %arg2) { 16 %ret = and i32 %arg1, %arg2 17 ret i32 %ret 18 } 19 20 define i64 @test_and_i64(i64 %arg1, i64 %arg2) { 21 %ret = and i64 %arg1, %arg2 22 ret i64 %ret 23 } 24 25... 26--- 27name: test_and_i8 28alignment: 16 29legalized: true 30regBankSelected: true 31registers: 32 - { id: 0, class: gpr, preferred-register: '' } 33 - { id: 1, class: gpr, preferred-register: '' } 34 - { id: 2, class: gpr, preferred-register: '' } 35liveins: 36fixedStack: 37stack: 38constants: 39body: | 40 bb.1 (%ir-block.0): 41 liveins: $edi, $esi 42 43 ; ALL-LABEL: name: test_and_i8 44 ; ALL: liveins: $edi, $esi 45 ; ALL-NEXT: {{ $}} 46 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil 47 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY $sil 48 ; ALL-NEXT: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[COPY]], [[COPY1]], implicit-def dead $eflags 49 ; ALL-NEXT: $al = COPY [[AND8rr]] 50 ; ALL-NEXT: RET 0, implicit $al 51 %0(s8) = COPY $dil 52 %1(s8) = COPY $sil 53 %2(s8) = G_AND %0, %1 54 $al = COPY %2(s8) 55 RET 0, implicit $al 56 57... 58--- 59name: test_and_i16 60alignment: 16 61legalized: true 62regBankSelected: true 63registers: 64 - { id: 0, class: gpr, preferred-register: '' } 65 - { id: 1, class: gpr, preferred-register: '' } 66 - { id: 2, class: gpr, preferred-register: '' } 67liveins: 68fixedStack: 69stack: 70constants: 71body: | 72 bb.1 (%ir-block.0): 73 liveins: $edi, $esi 74 75 ; ALL-LABEL: name: test_and_i16 76 ; ALL: liveins: $edi, $esi 77 ; ALL-NEXT: {{ $}} 78 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di 79 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si 80 ; ALL-NEXT: [[AND16rr:%[0-9]+]]:gr16 = AND16rr [[COPY]], [[COPY1]], implicit-def dead $eflags 81 ; ALL-NEXT: $ax = COPY [[AND16rr]] 82 ; ALL-NEXT: RET 0, implicit $ax 83 %0(s16) = COPY $di 84 %1(s16) = COPY $si 85 %2(s16) = G_AND %0, %1 86 $ax = COPY %2(s16) 87 RET 0, implicit $ax 88 89... 90--- 91name: test_and_i32 92alignment: 16 93legalized: true 94regBankSelected: true 95registers: 96 - { id: 0, class: gpr, preferred-register: '' } 97 - { id: 1, class: gpr, preferred-register: '' } 98 - { id: 2, class: gpr, preferred-register: '' } 99liveins: 100fixedStack: 101stack: 102constants: 103body: | 104 bb.1 (%ir-block.0): 105 liveins: $edi, $esi 106 107 ; ALL-LABEL: name: test_and_i32 108 ; ALL: liveins: $edi, $esi 109 ; ALL-NEXT: {{ $}} 110 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi 111 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 112 ; ALL-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[COPY]], [[COPY1]], implicit-def dead $eflags 113 ; ALL-NEXT: $eax = COPY [[AND32rr]] 114 ; ALL-NEXT: RET 0, implicit $eax 115 %0(s32) = COPY $edi 116 %1(s32) = COPY $esi 117 %2(s32) = G_AND %0, %1 118 $eax = COPY %2(s32) 119 RET 0, implicit $eax 120 121... 122--- 123name: test_and_i64 124alignment: 16 125legalized: true 126regBankSelected: true 127registers: 128 - { id: 0, class: gpr, preferred-register: '' } 129 - { id: 1, class: gpr, preferred-register: '' } 130 - { id: 2, class: gpr, preferred-register: '' } 131liveins: 132fixedStack: 133stack: 134constants: 135body: | 136 bb.1 (%ir-block.0): 137 liveins: $rdi, $rsi 138 139 ; ALL-LABEL: name: test_and_i64 140 ; ALL: liveins: $rdi, $rsi 141 ; ALL-NEXT: {{ $}} 142 ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 143 ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi 144 ; ALL-NEXT: [[AND64rr:%[0-9]+]]:gr64 = AND64rr [[COPY]], [[COPY1]], implicit-def dead $eflags 145 ; ALL-NEXT: $rax = COPY [[AND64rr]] 146 ; ALL-NEXT: RET 0, implicit $rax 147 %0(s64) = COPY $rdi 148 %1(s64) = COPY $rsi 149 %2(s64) = G_AND %0, %1 150 $rax = COPY %2(s64) 151 RET 0, implicit $rax 152 153... 154