xref: /llvm-project/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir (revision 373c343a77a7afaa07179db1754a52b620dfaf2e) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
3# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
4
5# test count trailing zeros for s16, s32, and s64
6
7---
8name:            test_cttz35
9alignment:       16
10legalized:       false
11regBankSelected: false
12registers:
13  - { id: 0, class: _, preferred-register: '' }
14body:             |
15  bb.1:
16    ; X64-LABEL: name: test_cttz35
17    ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
18    ; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
19    ; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
20    ; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
21    ; X64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738367
22    ; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[CTTZ_ZERO_UNDEF]], [[C1]]
23    ; X64-NEXT: RET 0, implicit [[AND]](s64)
24    ;
25    ; X86-LABEL: name: test_cttz35
26    ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
27    ; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
28    ; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
29    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
30    ; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[C]]
31    ; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[C1]]
32    ; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
33    ; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
34    ; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
35    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
36    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
37    ; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
38    ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
39    ; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
40    ; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
41    ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
42    ; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
43    ; X86-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
44    ; X86-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
45    ; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C4]]
46    ; X86-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C5]]
47    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND1]](s32), [[AND2]](s32)
48    ; X86-NEXT: RET 0, implicit [[MV]](s64)
49    %0(s64) = COPY $rdx
50    %1:_(s35) = G_TRUNC %0(s64)
51    %2:_(s35) = G_CTTZ %1
52    %3:_(s64) = G_ZEXT %2
53    RET 0, implicit %3
54...
55---
56name:            test_cttz8
57alignment:       16
58legalized:       false
59regBankSelected: false
60registers:
61  - { id: 0, class: _, preferred-register: '' }
62  - { id: 1, class: _, preferred-register: '' }
63body:             |
64  bb.1:
65    ; CHECK-LABEL: name: test_cttz8
66    ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
67    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[DEF]](s8)
68    ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_UNDEF [[ANYEXT]](s16)
69    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[CTTZ_ZERO_UNDEF]](s16)
70    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY [[TRUNC]](s8)
71    ; CHECK-NEXT: RET 0, implicit [[COPY]](s8)
72    %0:_(s8) = IMPLICIT_DEF
73    %1:_(s8) = G_CTTZ_ZERO_UNDEF %0
74    %2:_(s8) = COPY %1(s8)
75    RET 0, implicit %2
76...
77---
78name:            test_cttz64
79alignment:       16
80legalized:       false
81regBankSelected: false
82registers:
83  - { id: 0, class: _, preferred-register: '' }
84  - { id: 1, class: _, preferred-register: '' }
85body:             |
86  bb.1:
87    ; X64-LABEL: name: test_cttz64
88    ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
89    ; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[DEF]](s64)
90    ; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[CTTZ_ZERO_UNDEF]](s64)
91    ; X64-NEXT: RET 0, implicit [[COPY]](s64)
92    ;
93    ; X86-LABEL: name: test_cttz64
94    ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
95    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
96    ; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
97    ; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
98    ; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s32)
99    ; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
100    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C1]]
101    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
102    ; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
103    ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
104    ; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
105    ; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
106    ; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
107    ; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
108    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
109    ; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
110    ; X86-NEXT: RET 0, implicit [[COPY]](s64)
111    %0:_(s64) = IMPLICIT_DEF
112    %1:_(s64) = G_CTTZ_ZERO_UNDEF %0
113    %2:_(s64) = COPY %1(s64)
114    RET 0, implicit %2
115...
116---
117name:            test_cttz32
118alignment:       16
119legalized:       false
120regBankSelected: false
121registers:
122  - { id: 0, class: _, preferred-register: '' }
123  - { id: 1, class: _, preferred-register: '' }
124body:             |
125  bb.1:
126    ; CHECK-LABEL: name: test_cttz32
127    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
128    ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[DEF]](s32)
129    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
130    ; CHECK-NEXT: RET 0, implicit [[COPY]](s32)
131    %0:_(s32) = IMPLICIT_DEF
132    %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
133    %2:_(s32) = COPY %1(s32)
134    RET 0, implicit %2
135...
136---
137name:            test_cttz16
138alignment:       16
139legalized:       false
140regBankSelected: false
141registers:
142  - { id: 0, class: _, preferred-register: '' }
143  - { id: 1, class: _, preferred-register: '' }
144body:             |
145  bb.1:
146    ; CHECK-LABEL: name: test_cttz16
147    ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
148    ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s16) = G_CTTZ_ZERO_UNDEF [[DEF]](s16)
149    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY [[CTTZ_ZERO_UNDEF]](s16)
150    ; CHECK-NEXT: RET 0, implicit [[COPY]](s16)
151    %0:_(s16) = IMPLICIT_DEF
152    %1:_(s16) = G_CTTZ_ZERO_UNDEF %0
153    %2:_(s16) = COPY %1(s16)
154    RET 0, implicit %2
155...
156