xref: /llvm-project/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir (revision c63be92fc80c70d56f22abc5aa024ab957f8d4cd) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx               -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX1
3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f           -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX512F
4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX512BW
5
6# TODO: add tests for additional configuration after the legalization supported
7
8--- |
9  define void @test_sub_v64i8() {
10    %ret = sub <64 x i8> undef, undef
11    ret void
12  }
13
14  define void @test_sub_v32i16() {
15    %ret = sub <32 x i16> undef, undef
16    ret void
17  }
18
19  define void @test_sub_v16i32() {
20    %ret = sub <16 x i32> undef, undef
21    ret void
22  }
23
24  define void @test_sub_v8i64() {
25    %ret = sub <8 x i64> undef, undef
26    ret void
27  }
28
29...
30---
31name:            test_sub_v64i8
32alignment:       16
33legalized:       false
34regBankSelected: false
35registers:
36  - { id: 0, class: _ }
37  - { id: 1, class: _ }
38  - { id: 2, class: _ }
39body:             |
40  bb.1 (%ir-block.0):
41    liveins: $zmm0, $zmm1
42
43    ; AVX1-LABEL: name: test_sub_v64i8
44    ; AVX1: liveins: $zmm0, $zmm1
45    ; AVX1-NEXT: {{  $}}
46    ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
47    ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
48    ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>), [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
49    ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<16 x s8>), [[UV5:%[0-9]+]]:_(<16 x s8>), [[UV6:%[0-9]+]]:_(<16 x s8>), [[UV7:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
50    ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV]], [[UV4]]
51    ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV1]], [[UV5]]
52    ; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV2]], [[UV6]]
53    ; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV3]], [[UV7]]
54    ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[SUB]](<16 x s8>), [[SUB1]](<16 x s8>), [[SUB2]](<16 x s8>), [[SUB3]](<16 x s8>)
55    ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
56    ; AVX1-NEXT: RET 0
57    ;
58    ; AVX512F-LABEL: name: test_sub_v64i8
59    ; AVX512F: liveins: $zmm0, $zmm1
60    ; AVX512F-NEXT: {{  $}}
61    ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
62    ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
63    ; AVX512F-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
64    ; AVX512F-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
65    ; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[UV]], [[UV2]]
66    ; AVX512F-NEXT: [[SUB1:%[0-9]+]]:_(<32 x s8>) = G_SUB [[UV1]], [[UV3]]
67    ; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[SUB]](<32 x s8>), [[SUB1]](<32 x s8>)
68    ; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
69    ; AVX512F-NEXT: RET 0
70    ;
71    ; AVX512BW-LABEL: name: test_sub_v64i8
72    ; AVX512BW: liveins: $zmm0, $zmm1
73    ; AVX512BW-NEXT: {{  $}}
74    ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
75    ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
76    ; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
77    ; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<64 x s8>)
78    ; AVX512BW-NEXT: RET 0
79    %0(<64 x s8>) = IMPLICIT_DEF
80    %1(<64 x s8>) = IMPLICIT_DEF
81    %2(<64 x s8>) = G_SUB %0, %1
82    $zmm0 = COPY %2
83    RET 0
84
85...
86---
87name:            test_sub_v32i16
88alignment:       16
89legalized:       false
90regBankSelected: false
91registers:
92  - { id: 0, class: _ }
93  - { id: 1, class: _ }
94  - { id: 2, class: _ }
95body:             |
96  bb.1 (%ir-block.0):
97    liveins: $zmm0, $zmm1
98
99    ; AVX1-LABEL: name: test_sub_v32i16
100    ; AVX1: liveins: $zmm0, $zmm1
101    ; AVX1-NEXT: {{  $}}
102    ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
103    ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
104    ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>), [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
105    ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<8 x s16>), [[UV5:%[0-9]+]]:_(<8 x s16>), [[UV6:%[0-9]+]]:_(<8 x s16>), [[UV7:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
106    ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV]], [[UV4]]
107    ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV1]], [[UV5]]
108    ; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV2]], [[UV6]]
109    ; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV3]], [[UV7]]
110    ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[SUB]](<8 x s16>), [[SUB1]](<8 x s16>), [[SUB2]](<8 x s16>), [[SUB3]](<8 x s16>)
111    ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
112    ; AVX1-NEXT: RET 0
113    ;
114    ; AVX512F-LABEL: name: test_sub_v32i16
115    ; AVX512F: liveins: $zmm0, $zmm1
116    ; AVX512F-NEXT: {{  $}}
117    ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
118    ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
119    ; AVX512F-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
120    ; AVX512F-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
121    ; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[UV]], [[UV2]]
122    ; AVX512F-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s16>) = G_SUB [[UV1]], [[UV3]]
123    ; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[SUB]](<16 x s16>), [[SUB1]](<16 x s16>)
124    ; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
125    ; AVX512F-NEXT: RET 0
126    ;
127    ; AVX512BW-LABEL: name: test_sub_v32i16
128    ; AVX512BW: liveins: $zmm0, $zmm1
129    ; AVX512BW-NEXT: {{  $}}
130    ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
131    ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
132    ; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
133    ; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<32 x s16>)
134    ; AVX512BW-NEXT: RET 0
135    %0(<32 x s16>) = IMPLICIT_DEF
136    %1(<32 x s16>) = IMPLICIT_DEF
137    %2(<32 x s16>) = G_SUB %0, %1
138    $zmm0 = COPY %2
139    RET 0
140
141...
142---
143name:            test_sub_v16i32
144alignment:       16
145legalized:       false
146regBankSelected: false
147registers:
148  - { id: 0, class: _ }
149  - { id: 1, class: _ }
150  - { id: 2, class: _ }
151body:             |
152  bb.1 (%ir-block.0):
153    liveins: $zmm0, $zmm1
154
155    ; AVX1-LABEL: name: test_sub_v16i32
156    ; AVX1: liveins: $zmm0, $zmm1
157    ; AVX1-NEXT: {{  $}}
158    ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
159    ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
160    ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>), [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
161    ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<4 x s32>), [[UV5:%[0-9]+]]:_(<4 x s32>), [[UV6:%[0-9]+]]:_(<4 x s32>), [[UV7:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
162    ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV]], [[UV4]]
163    ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV1]], [[UV5]]
164    ; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV2]], [[UV6]]
165    ; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV3]], [[UV7]]
166    ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[SUB]](<4 x s32>), [[SUB1]](<4 x s32>), [[SUB2]](<4 x s32>), [[SUB3]](<4 x s32>)
167    ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
168    ; AVX1-NEXT: RET 0
169    ;
170    ; AVX512F-LABEL: name: test_sub_v16i32
171    ; AVX512F: liveins: $zmm0, $zmm1
172    ; AVX512F-NEXT: {{  $}}
173    ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
174    ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
175    ; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
176    ; AVX512F-NEXT: $zmm0 = COPY [[SUB]](<16 x s32>)
177    ; AVX512F-NEXT: RET 0
178    ;
179    ; AVX512BW-LABEL: name: test_sub_v16i32
180    ; AVX512BW: liveins: $zmm0, $zmm1
181    ; AVX512BW-NEXT: {{  $}}
182    ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
183    ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
184    ; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
185    ; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<16 x s32>)
186    ; AVX512BW-NEXT: RET 0
187    %0(<16 x s32>) = IMPLICIT_DEF
188    %1(<16 x s32>) = IMPLICIT_DEF
189    %2(<16 x s32>) = G_SUB %0, %1
190    $zmm0 = COPY %2
191    RET 0
192
193...
194---
195name:            test_sub_v8i64
196alignment:       16
197legalized:       false
198regBankSelected: false
199registers:
200  - { id: 0, class: _ }
201  - { id: 1, class: _ }
202  - { id: 2, class: _ }
203body:             |
204  bb.1 (%ir-block.0):
205    liveins: $zmm0, $zmm1
206
207    ; AVX1-LABEL: name: test_sub_v8i64
208    ; AVX1: liveins: $zmm0, $zmm1
209    ; AVX1-NEXT: {{  $}}
210    ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
211    ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
212    ; AVX1-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>), [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
213    ; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<2 x s64>), [[UV5:%[0-9]+]]:_(<2 x s64>), [[UV6:%[0-9]+]]:_(<2 x s64>), [[UV7:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
214    ; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV]], [[UV4]]
215    ; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV1]], [[UV5]]
216    ; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV2]], [[UV6]]
217    ; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV3]], [[UV7]]
218    ; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[SUB]](<2 x s64>), [[SUB1]](<2 x s64>), [[SUB2]](<2 x s64>), [[SUB3]](<2 x s64>)
219    ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
220    ; AVX1-NEXT: RET 0
221    ;
222    ; AVX512F-LABEL: name: test_sub_v8i64
223    ; AVX512F: liveins: $zmm0, $zmm1
224    ; AVX512F-NEXT: {{  $}}
225    ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
226    ; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
227    ; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
228    ; AVX512F-NEXT: $zmm0 = COPY [[SUB]](<8 x s64>)
229    ; AVX512F-NEXT: RET 0
230    ;
231    ; AVX512BW-LABEL: name: test_sub_v8i64
232    ; AVX512BW: liveins: $zmm0, $zmm1
233    ; AVX512BW-NEXT: {{  $}}
234    ; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
235    ; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
236    ; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
237    ; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<8 x s64>)
238    ; AVX512BW-NEXT: RET 0
239    %0(<8 x s64>) = IMPLICIT_DEF
240    %1(<8 x s64>) = IMPLICIT_DEF
241    %2(<8 x s64>) = G_SUB %0, %1
242    $zmm0 = COPY %2
243    RET 0
244
245...
246