1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64 3# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86 4 5--- | 6 7 define void @test_or_i1() { ret void} 8 define void @test_or_i8() { ret void } 9 define void @test_or_i16() { ret void } 10 define void @test_or_i27() { ret void } 11 define void @test_or_i32() { ret void } 12 define void @test_or_i42() { ret void } 13 define void @test_or_i64() { ret void } 14 15... 16--- 17name: test_or_i1 18alignment: 16 19legalized: false 20regBankSelected: false 21registers: 22 - { id: 0, class: _, preferred-register: '' } 23 - { id: 1, class: _, preferred-register: '' } 24 - { id: 2, class: _, preferred-register: '' } 25body: | 26 bb.1 (%ir-block.0): 27 ; CHECK-LABEL: name: test_or_i1 28 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx 29 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 30 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 31 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]] 32 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s8) 33 ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32) 34 ; CHECK-NEXT: RET 0 35 %0(s32) = COPY $edx 36 %1(s1) = G_TRUNC %0(s32) 37 %2(s1) = G_OR %1, %1 38 %3:_(s32) = G_ANYEXT %2 39 $eax = COPY %3 40 RET 0 41... 42--- 43name: test_or_i8 44alignment: 16 45legalized: false 46regBankSelected: false 47registers: 48 - { id: 0, class: _, preferred-register: '' } 49 - { id: 1, class: _, preferred-register: '' } 50 - { id: 2, class: _, preferred-register: '' } 51body: | 52 bb.1 (%ir-block.0): 53 ; CHECK-LABEL: name: test_or_i8 54 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx 55 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 56 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC]] 57 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s8) 58 ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32) 59 ; CHECK-NEXT: RET 0 60 %0(s32) = COPY $edx 61 %1(s8) = G_TRUNC %0(s32) 62 %2(s8) = G_OR %1, %1 63 %3:_(s32) = G_ANYEXT %2 64 $eax = COPY %3 65 RET 0 66... 67--- 68name: test_or_i16 69alignment: 16 70legalized: false 71regBankSelected: false 72registers: 73 - { id: 0, class: _ } 74 - { id: 1, class: _ } 75 - { id: 2, class: _ } 76body: | 77 bb.1 (%ir-block.0): 78 ; CHECK-LABEL: name: test_or_i16 79 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx 80 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 81 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC]] 82 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) 83 ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32) 84 ; CHECK-NEXT: RET 0 85 %0(s32) = COPY $edx 86 %1(s16) = G_TRUNC %0(s32) 87 %2(s16) = G_OR %1, %1 88 %3:_(s32) = G_ANYEXT %2 89 $eax = COPY %3 90 RET 0 91... 92--- 93name: test_or_i27 94alignment: 16 95legalized: false 96regBankSelected: false 97registers: 98 - { id: 0, class: _ } 99 - { id: 1, class: _ } 100 - { id: 2, class: _ } 101body: | 102 bb.1 (%ir-block.0): 103 ; CHECK-LABEL: name: test_or_i27 104 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx 105 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY]] 106 ; CHECK-NEXT: $eax = COPY [[OR]](s32) 107 ; CHECK-NEXT: RET 0 108 %0(s32) = COPY $edx 109 %1(s27) = G_TRUNC %0(s32) 110 %2(s27) = G_OR %1, %1 111 %3:_(s32) = G_ANYEXT %2 112 $eax = COPY %3 113 RET 0 114... 115--- 116name: test_or_i32 117alignment: 16 118legalized: false 119regBankSelected: false 120registers: 121 - { id: 0, class: _ } 122 - { id: 1, class: _ } 123 - { id: 2, class: _ } 124body: | 125 bb.1 (%ir-block.0): 126 ; CHECK-LABEL: name: test_or_i32 127 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF 128 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF 129 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF1]] 130 ; CHECK-NEXT: $eax = COPY [[OR]](s32) 131 ; CHECK-NEXT: RET 0 132 %0(s32) = IMPLICIT_DEF 133 %1(s32) = IMPLICIT_DEF 134 %2(s32) = G_OR %0, %1 135 $eax = COPY %2 136 RET 0 137... 138--- 139name: test_or_i42 140alignment: 16 141legalized: false 142regBankSelected: false 143registers: 144 - { id: 0, class: _ } 145 - { id: 1, class: _ } 146 - { id: 2, class: _ } 147body: | 148 bb.1 (%ir-block.0): 149 ; X64-LABEL: name: test_or_i42 150 ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx 151 ; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY]] 152 ; X64-NEXT: $rax = COPY [[OR]](s64) 153 ; X64-NEXT: RET 0 154 ; X86-LABEL: name: test_or_i42 155 ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx 156 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 157 ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 158 ; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV2]] 159 ; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[UV3]] 160 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32) 161 ; X86-NEXT: $rax = COPY [[MV]](s64) 162 ; X86-NEXT: RET 0 163 %0(s64) = COPY $rdx 164 %1(s42) = G_TRUNC %0(s64) 165 %2(s42) = G_OR %1, %1 166 %3:_(s64) = G_ANYEXT %2 167 $rax = COPY %3 168 RET 0 169... 170--- 171name: test_or_i64 172alignment: 16 173legalized: false 174regBankSelected: false 175registers: 176 - { id: 0, class: _ } 177 - { id: 1, class: _ } 178 - { id: 2, class: _ } 179body: | 180 bb.1 (%ir-block.0): 181 ; X64-LABEL: name: test_or_i64 182 ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF 183 ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF 184 ; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF1]] 185 ; X64-NEXT: $rax = COPY [[OR]](s64) 186 ; X64-NEXT: RET 0 187 ; X86-LABEL: name: test_or_i64 188 ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF 189 ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF 190 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64) 191 ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64) 192 ; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV2]] 193 ; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[UV3]] 194 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32) 195 ; X86-NEXT: $rax = COPY [[MV]](s64) 196 ; X86-NEXT: RET 0 197 %0(s64) = IMPLICIT_DEF 198 %1(s64) = IMPLICIT_DEF 199 %2(s64) = G_OR %0, %1 200 $rax = COPY %2 201 RET 0 202... 203