1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64 3# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86 4 5--- | 6 define void @test_mul_i1() { ret void } 7 8 define i8 @test_mul_i8(i8 %arg1, i8 %arg2) { 9 %ret = mul i8 %arg1, %arg2 10 ret i8 %ret 11 } 12 13 define i16 @test_mul_i16(i16 %arg1, i16 %arg2) { 14 %ret = mul i16 %arg1, %arg2 15 ret i16 %ret 16 } 17 18 define i27 @test_mul_i27(i27 %arg1, i27 %arg2) { 19 %ret = mul i27 %arg1, %arg2 20 ret i27 %ret 21 } 22 23 define i32 @test_mul_i32(i32 %arg1, i32 %arg2) { 24 %ret = mul i32 %arg1, %arg2 25 ret i32 %ret 26 } 27 28 define i42 @test_mul_i42(i42 %arg1, i42 %arg2) { 29 %ret = mul i42 %arg1, %arg2 30 ret i42 %ret 31 } 32 33 define i64 @test_mul_i64(i64 %arg1, i64 %arg2) { 34 %ret = mul i64 %arg1, %arg2 35 ret i64 %ret 36 } 37... 38--- 39name: test_mul_i1 40alignment: 16 41legalized: false 42regBankSelected: false 43registers: 44 - { id: 0, class: _, preferred-register: '' } 45 - { id: 1, class: _, preferred-register: '' } 46 - { id: 2, class: _, preferred-register: '' } 47body: | 48 bb.1 (%ir-block.0): 49 50 ; CHECK-LABEL: name: test_mul_i1 51 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx 52 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 53 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 54 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[TRUNC]], [[TRUNC1]] 55 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF 56 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 57 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[MUL]], [[C]] 58 ; CHECK-NEXT: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1)) 59 ; CHECK-NEXT: RET 0 60 %0(s32) = COPY $edx 61 %1(s1) = G_TRUNC %0(s32) 62 %2(s1) = G_MUL %1, %1 63 %3:_(p0) = G_IMPLICIT_DEF 64 G_STORE %2, %3 :: (store (s1)) 65 RET 0 66... 67--- 68name: test_mul_i8 69alignment: 16 70legalized: false 71regBankSelected: false 72registers: 73 - { id: 0, class: _ } 74 - { id: 1, class: _ } 75 - { id: 2, class: _ } 76body: | 77 bb.1 (%ir-block.0): 78 liveins: $edi, $esi 79 80 ; CHECK-LABEL: name: test_mul_i8 81 ; CHECK: liveins: $edi, $esi 82 ; CHECK-NEXT: {{ $}} 83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dl 84 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $sil 85 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[COPY]], [[COPY1]] 86 ; CHECK-NEXT: $al = COPY [[MUL]](s8) 87 ; CHECK-NEXT: RET 0, implicit $al 88 %0(s8) = COPY $dl 89 %1(s8) = COPY $sil 90 %2(s8) = G_MUL %0, %1 91 $al = COPY %2(s8) 92 RET 0, implicit $al 93... 94--- 95name: test_mul_i16 96alignment: 16 97legalized: false 98regBankSelected: false 99registers: 100 - { id: 0, class: _ } 101 - { id: 1, class: _ } 102 - { id: 2, class: _ } 103body: | 104 bb.1 (%ir-block.0): 105 liveins: $edi, $esi 106 107 ; CHECK-LABEL: name: test_mul_i16 108 ; CHECK: liveins: $edi, $esi 109 ; CHECK-NEXT: {{ $}} 110 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di 111 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $si 112 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[COPY]], [[COPY1]] 113 ; CHECK-NEXT: $ax = COPY [[MUL]](s16) 114 ; CHECK-NEXT: RET 0, implicit $ax 115 %0(s16) = COPY $di 116 %1(s16) = COPY $si 117 %2(s16) = G_MUL %0, %1 118 $ax = COPY %2(s16) 119 RET 0, implicit $ax 120... 121--- 122name: test_mul_i27 123alignment: 16 124legalized: false 125regBankSelected: false 126registers: 127 - { id: 0, class: _ } 128 - { id: 1, class: _ } 129 - { id: 2, class: _ } 130body: | 131 bb.1 (%ir-block.0): 132 133 ; 134 ; 135 ; CHECK-LABEL: name: test_mul_i27 136 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx 137 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY]] 138 ; CHECK-NEXT: $eax = COPY [[MUL]](s32) 139 ; CHECK-NEXT: RET 0 140 %0(s32) = COPY $edx 141 %1(s27) = G_TRUNC %0(s32) 142 %2(s27) = G_MUL %1, %1 143 %3:_(s32) = G_ANYEXT %2 144 $eax = COPY %3 145 RET 0 146... 147--- 148 149name: test_mul_i32 150alignment: 16 151legalized: false 152regBankSelected: false 153registers: 154 - { id: 0, class: _ } 155 - { id: 1, class: _ } 156 - { id: 2, class: _ } 157body: | 158 bb.1 (%ir-block.0): 159 liveins: $edi, $esi 160 161 ; CHECK-LABEL: name: test_mul_i32 162 ; CHECK: liveins: $edi, $esi 163 ; CHECK-NEXT: {{ $}} 164 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 165 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi 166 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]] 167 ; CHECK-NEXT: $eax = COPY [[MUL]](s32) 168 ; CHECK-NEXT: RET 0, implicit $eax 169 %0(s32) = COPY $edi 170 %1(s32) = COPY $esi 171 %2(s32) = G_MUL %0, %1 172 $eax = COPY %2(s32) 173 RET 0, implicit $eax 174... 175--- 176name: test_mul_i42 177alignment: 16 178legalized: false 179regBankSelected: false 180registers: 181 - { id: 0, class: _ } 182 - { id: 1, class: _ } 183 - { id: 2, class: _ } 184body: | 185 bb.1 (%ir-block.0): 186 liveins: $rdi, $rsi 187 188 ; X64-LABEL: name: test_mul_i42 189 ; X64: liveins: $rdi, $rsi 190 ; X64-NEXT: {{ $}} 191 ; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx 192 ; X64-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY]] 193 ; X64-NEXT: $rax = COPY [[MUL]](s64) 194 ; X64-NEXT: RET 0 195 ; X86-LABEL: name: test_mul_i42 196 ; X86: liveins: $rdi, $rsi 197 ; X86-NEXT: {{ $}} 198 ; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx 199 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 200 ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 201 ; X86-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]] 202 ; X86-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]] 203 ; X86-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]] 204 ; X86-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[UV]], [[UV2]] 205 ; X86-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]] 206 ; X86-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]] 207 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL]](s32), [[ADD1]](s32) 208 ; X86-NEXT: $rax = COPY [[MV]](s64) 209 ; X86-NEXT: RET 0 210 %0(s64) = COPY $rdx 211 %1(s42) = G_TRUNC %0(s64) 212 %2(s42) = G_MUL %1, %1 213 %3:_(s64) = G_ANYEXT %2 214 $rax = COPY %3 215 RET 0 216... 217--- 218name: test_mul_i64 219alignment: 16 220legalized: false 221regBankSelected: false 222registers: 223 - { id: 0, class: _ } 224 - { id: 1, class: _ } 225 - { id: 2, class: _ } 226body: | 227 bb.1 (%ir-block.0): 228 liveins: $rdi, $rsi 229 230 ; X64-LABEL: name: test_mul_i64 231 ; X64: liveins: $rdi, $rsi 232 ; X64-NEXT: {{ $}} 233 ; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 234 ; X64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 235 ; X64-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]] 236 ; X64-NEXT: $rax = COPY [[MUL]](s64) 237 ; X64-NEXT: RET 0, implicit $rax 238 ; X86-LABEL: name: test_mul_i64 239 ; X86: liveins: $rdi, $rsi 240 ; X86-NEXT: {{ $}} 241 ; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi 242 ; X86-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi 243 ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) 244 ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) 245 ; X86-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]] 246 ; X86-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]] 247 ; X86-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]] 248 ; X86-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[UV]], [[UV2]] 249 ; X86-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]] 250 ; X86-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]] 251 ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL]](s32), [[ADD1]](s32) 252 ; X86-NEXT: $rax = COPY [[MV]](s64) 253 ; X86-NEXT: RET 0, implicit $rax 254 %0(s64) = COPY $rdi 255 %1(s64) = COPY $rsi 256 %2(s64) = G_MUL %0, %1 257 $rax = COPY %2(s64) 258 RET 0, implicit $rax 259... 260