1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s 3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s 4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s 5 6--- | 7 define void @test_and_v16i8() { 8 %ret = and <16 x i8> undef, undef 9 ret void 10 } 11 12 define void @test_and_v8i16() { 13 %ret = and <8 x i16> undef, undef 14 ret void 15 } 16 17 define void @test_and_v4i32() { 18 %ret = and <4 x i32> undef, undef 19 ret void 20 } 21 22 define void @test_and_v2i64() { 23 %ret = and <2 x i64> undef, undef 24 ret void 25 } 26... 27--- 28name: test_and_v16i8 29alignment: 16 30legalized: false 31regBankSelected: false 32registers: 33 - { id: 0, class: _ } 34 - { id: 1, class: _ } 35 - { id: 2, class: _ } 36body: | 37 bb.1 (%ir-block.0): 38 liveins: $xmm0, $xmm1 39 40 ; CHECK-LABEL: name: test_and_v16i8 41 ; CHECK: liveins: $xmm0, $xmm1 42 ; CHECK-NEXT: {{ $}} 43 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF 44 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF 45 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[DEF]], [[DEF1]] 46 ; CHECK-NEXT: $xmm0 = COPY [[AND]](<16 x s8>) 47 ; CHECK-NEXT: RET 0 48 %0(<16 x s8>) = IMPLICIT_DEF 49 %1(<16 x s8>) = IMPLICIT_DEF 50 %2(<16 x s8>) = G_AND %0, %1 51 $xmm0 = COPY %2 52 RET 0 53... 54--- 55name: test_and_v8i16 56alignment: 16 57legalized: false 58regBankSelected: false 59registers: 60 - { id: 0, class: _ } 61 - { id: 1, class: _ } 62 - { id: 2, class: _ } 63body: | 64 bb.1 (%ir-block.0): 65 liveins: $xmm0, $xmm1 66 67 ; CHECK-LABEL: name: test_and_v8i16 68 ; CHECK: liveins: $xmm0, $xmm1 69 ; CHECK-NEXT: {{ $}} 70 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF 71 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF 72 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[DEF]], [[DEF1]] 73 ; CHECK-NEXT: $xmm0 = COPY [[AND]](<8 x s16>) 74 ; CHECK-NEXT: RET 0 75 %0(<8 x s16>) = IMPLICIT_DEF 76 %1(<8 x s16>) = IMPLICIT_DEF 77 %2(<8 x s16>) = G_AND %0, %1 78 $xmm0 = COPY %2 79 RET 0 80... 81--- 82name: test_and_v4i32 83alignment: 16 84legalized: false 85regBankSelected: false 86registers: 87 - { id: 0, class: _ } 88 - { id: 1, class: _ } 89 - { id: 2, class: _ } 90body: | 91 bb.1 (%ir-block.0): 92 liveins: $xmm0, $xmm1 93 94 ; CHECK-LABEL: name: test_and_v4i32 95 ; CHECK: liveins: $xmm0, $xmm1 96 ; CHECK-NEXT: {{ $}} 97 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF 98 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF 99 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[DEF]], [[DEF1]] 100 ; CHECK-NEXT: $xmm0 = COPY [[AND]](<4 x s32>) 101 ; CHECK-NEXT: RET 0 102 %0(<4 x s32>) = IMPLICIT_DEF 103 %1(<4 x s32>) = IMPLICIT_DEF 104 %2(<4 x s32>) = G_AND %0, %1 105 $xmm0 = COPY %2 106 RET 0 107... 108--- 109name: test_and_v2i64 110alignment: 16 111legalized: false 112regBankSelected: false 113registers: 114 - { id: 0, class: _ } 115 - { id: 1, class: _ } 116 - { id: 2, class: _ } 117body: | 118 bb.1 (%ir-block.0): 119 liveins: $xmm0, $xmm1 120 121 ; CHECK-LABEL: name: test_and_v2i64 122 ; CHECK: liveins: $xmm0, $xmm1 123 ; CHECK-NEXT: {{ $}} 124 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF 125 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF 126 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[DEF1]] 127 ; CHECK-NEXT: $xmm0 = COPY [[AND]](<2 x s64>) 128 ; CHECK-NEXT: RET 0 129 %0(<2 x s64>) = IMPLICIT_DEF 130 %1(<2 x s64>) = IMPLICIT_DEF 131 %2(<2 x s64>) = G_AND %0, %1 132 $xmm0 = COPY %2 133 RET 0 134... 135