xref: /llvm-project/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir (revision c63be92fc80c70d56f22abc5aa024ab957f8d4cd) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
3# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
4
5--- |
6
7  define void @test_add_i1() { ret void}
8  define void @test_add_i8() { ret void }
9  define void @test_add_i16() { ret void }
10  define void @test_add_i27() { ret void }
11  define void @test_add_i32() { ret void }
12  define void @test_add_i42() { ret void }
13  define void @test_add_i64() { ret void }
14  define void @test_add_i128() { ret void }
15
16...
17---
18name:            test_add_i1
19alignment:       16
20legalized:       false
21regBankSelected: false
22registers:
23  - { id: 0, class: _, preferred-register: '' }
24  - { id: 1, class: _, preferred-register: '' }
25  - { id: 2, class: _, preferred-register: '' }
26body:             |
27  bb.1 (%ir-block.0):
28    ; CHECK-LABEL: name: test_add_i1
29    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
30    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
31    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
32    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
33    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
34    ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
35    ; CHECK-NEXT: RET 0
36    %0(s32) = COPY $edx
37    %1(s1) = G_TRUNC %0(s32)
38    %2(s1) = G_ADD %1, %1
39    %3:_(s32) = G_ANYEXT %2
40    $eax = COPY %3
41    RET 0
42...
43---
44name:            test_add_i8
45alignment:       16
46legalized:       false
47regBankSelected: false
48registers:
49  - { id: 0, class: _, preferred-register: '' }
50  - { id: 1, class: _, preferred-register: '' }
51  - { id: 2, class: _, preferred-register: '' }
52body:             |
53  bb.1 (%ir-block.0):
54    ; CHECK-LABEL: name: test_add_i8
55    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
56    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
57    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC]]
58    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
59    ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
60    ; CHECK-NEXT: RET 0
61    %0(s32) = COPY $edx
62    %1(s8) = G_TRUNC %0(s32)
63    %2(s8) = G_ADD %1, %1
64    %3:_(s32) = G_ANYEXT %2
65    $eax = COPY %3
66    RET 0
67...
68---
69name:            test_add_i16
70alignment:       16
71legalized:       false
72regBankSelected: false
73registers:
74  - { id: 0, class: _ }
75  - { id: 1, class: _ }
76  - { id: 2, class: _ }
77body:             |
78  bb.1 (%ir-block.0):
79    ; CHECK-LABEL: name: test_add_i16
80    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
81    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
82    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
83    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
84    ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
85    ; CHECK-NEXT: RET 0
86    %0(s32) = COPY $edx
87    %1(s16) = G_TRUNC %0(s32)
88    %2(s16) = G_ADD %1, %1
89    %3:_(s32) = G_ANYEXT %2
90    $eax = COPY %3
91    RET 0
92...
93---
94name:            test_add_i27
95alignment:       16
96legalized:       false
97regBankSelected: false
98registers:
99  - { id: 0, class: _ }
100  - { id: 1, class: _ }
101  - { id: 2, class: _ }
102body:             |
103  bb.1 (%ir-block.0):
104    ; CHECK-LABEL: name: test_add_i27
105    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
106    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
107    ; CHECK-NEXT: $eax = COPY [[ADD]](s32)
108    ; CHECK-NEXT: RET 0
109    %0(s32) = COPY $edx
110    %1(s27) = G_TRUNC %0(s32)
111    %2(s27) = G_ADD %1, %1
112    %3:_(s32) = G_ANYEXT %2
113    $eax = COPY %3
114    RET 0
115...
116---
117name:            test_add_i32
118alignment:       16
119legalized:       false
120regBankSelected: false
121registers:
122  - { id: 0, class: _ }
123  - { id: 1, class: _ }
124  - { id: 2, class: _ }
125body:             |
126  bb.1 (%ir-block.0):
127    ; CHECK-LABEL: name: test_add_i32
128    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
129    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
130    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
131    ; CHECK-NEXT: $eax = COPY [[ADD]](s32)
132    ; CHECK-NEXT: RET 0
133    %0(s32) = IMPLICIT_DEF
134    %1(s32) = IMPLICIT_DEF
135    %2(s32) = G_ADD %0, %1
136    $eax = COPY %2
137    RET 0
138...
139---
140name:            test_add_i42
141alignment:       16
142legalized:       false
143regBankSelected: false
144registers:
145  - { id: 0, class: _ }
146  - { id: 1, class: _ }
147  - { id: 2, class: _ }
148body:             |
149  bb.1 (%ir-block.0):
150    ; X64-LABEL: name: test_add_i42
151    ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
152    ; X64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY]]
153    ; X64-NEXT: $rax = COPY [[ADD]](s64)
154    ; X64-NEXT: RET 0
155    ;
156    ; X86-LABEL: name: test_add_i42
157    ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
158    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
159    ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
160    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
161    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
162    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
163    ; X86-NEXT: $rax = COPY [[MV]](s64)
164    ; X86-NEXT: RET 0
165    %0(s64) = COPY $rdx
166    %1(s42) = G_TRUNC %0(s64)
167    %2(s42) = G_ADD %1, %1
168    %3:_(s64) = G_ANYEXT %2
169    $rax = COPY %3
170    RET 0
171...
172---
173name:            test_add_i64
174alignment:       16
175legalized:       false
176regBankSelected: false
177registers:
178  - { id: 0, class: _ }
179  - { id: 1, class: _ }
180  - { id: 2, class: _ }
181body:             |
182  bb.1 (%ir-block.0):
183    ; X64-LABEL: name: test_add_i64
184    ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
185    ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
186    ; X64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[DEF]], [[DEF1]]
187    ; X64-NEXT: $rax = COPY [[ADD]](s64)
188    ; X64-NEXT: RET 0
189    ;
190    ; X86-LABEL: name: test_add_i64
191    ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
192    ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
193    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
194    ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
195    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
196    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
197    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
198    ; X86-NEXT: $rax = COPY [[MV]](s64)
199    ; X86-NEXT: RET 0
200    %0(s64) = IMPLICIT_DEF
201    %1(s64) = IMPLICIT_DEF
202    %2(s64) = G_ADD %0, %1
203    $rax = COPY %2
204    RET 0
205...
206---
207name:            test_add_i128
208alignment:       16
209legalized:       false
210regBankSelected: false
211registers:
212  - { id: 0, class: _ }
213  - { id: 1, class: _ }
214  - { id: 2, class: _ }
215body:             |
216  bb.1 (%ir-block.0):
217    ; X64-LABEL: name: test_add_i128
218    ; X64: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF
219    ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
220    ; X64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](s128)
221    ; X64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF1]](s128)
222    ; X64-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
223    ; X64-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
224    ; X64-NEXT: $rax = COPY [[UADDO]](s64)
225    ; X64-NEXT: $rdx = COPY [[UADDE]](s64)
226    ; X64-NEXT: RET 0
227    ;
228    ; X86-LABEL: name: test_add_i128
229    ; X86: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF
230    ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
231    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
232    ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
233    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV4]]
234    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]]
235    ; X86-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]]
236    ; X86-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]]
237    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
238    ; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE2]](s32), [[UADDE4]](s32)
239    ; X86-NEXT: $rax = COPY [[MV]](s64)
240    ; X86-NEXT: $rdx = COPY [[MV1]](s64)
241    ; X86-NEXT: RET 0
242    %0(s128) = IMPLICIT_DEF
243    %1(s128) = IMPLICIT_DEF
244    %2(s128) = G_ADD %0, %1
245    %3:_(s64), %4:_(s64) = G_UNMERGE_VALUES %2(s128)
246    $rax = COPY %3
247    $rdx = COPY %4
248    RET 0
249...
250