1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL 3 4--- | 5 define void @test_add_v16i8() { 6 %ret = add <16 x i8> undef, undef 7 ret void 8 } 9 10 define void @test_add_v8i16() { 11 %ret = add <8 x i16> undef, undef 12 ret void 13 } 14 15 define void @test_add_v4i32() { 16 %ret = add <4 x i32> undef, undef 17 ret void 18 } 19 20 define void @test_add_v2i64() { 21 %ret = add <2 x i64> undef, undef 22 ret void 23 } 24... 25--- 26name: test_add_v16i8 27alignment: 16 28legalized: false 29regBankSelected: false 30registers: 31 - { id: 0, class: _ } 32 - { id: 1, class: _ } 33 - { id: 2, class: _ } 34body: | 35 bb.1 (%ir-block.0): 36 liveins: $xmm0, $xmm1 37 38 ; ALL-LABEL: name: test_add_v16i8 39 ; ALL: liveins: $xmm0, $xmm1 40 ; ALL-NEXT: {{ $}} 41 ; ALL-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF 42 ; ALL-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF 43 ; ALL-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]] 44 ; ALL-NEXT: $xmm0 = COPY [[ADD]](<16 x s8>) 45 ; ALL-NEXT: RET 0 46 %0(<16 x s8>) = IMPLICIT_DEF 47 %1(<16 x s8>) = IMPLICIT_DEF 48 %2(<16 x s8>) = G_ADD %0, %1 49 $xmm0 = COPY %2 50 RET 0 51 52... 53--- 54name: test_add_v8i16 55alignment: 16 56legalized: false 57regBankSelected: false 58registers: 59 - { id: 0, class: _ } 60 - { id: 1, class: _ } 61 - { id: 2, class: _ } 62body: | 63 bb.1 (%ir-block.0): 64 liveins: $xmm0, $xmm1 65 66 ; ALL-LABEL: name: test_add_v8i16 67 ; ALL: liveins: $xmm0, $xmm1 68 ; ALL-NEXT: {{ $}} 69 ; ALL-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF 70 ; ALL-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF 71 ; ALL-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]] 72 ; ALL-NEXT: $xmm0 = COPY [[ADD]](<8 x s16>) 73 ; ALL-NEXT: RET 0 74 %0(<8 x s16>) = IMPLICIT_DEF 75 %1(<8 x s16>) = IMPLICIT_DEF 76 %2(<8 x s16>) = G_ADD %0, %1 77 $xmm0 = COPY %2 78 RET 0 79 80... 81--- 82name: test_add_v4i32 83alignment: 16 84legalized: false 85regBankSelected: false 86registers: 87 - { id: 0, class: _ } 88 - { id: 1, class: _ } 89 - { id: 2, class: _ } 90body: | 91 bb.1 (%ir-block.0): 92 liveins: $xmm0, $xmm1 93 94 ; ALL-LABEL: name: test_add_v4i32 95 ; ALL: liveins: $xmm0, $xmm1 96 ; ALL-NEXT: {{ $}} 97 ; ALL-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF 98 ; ALL-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF 99 ; ALL-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]] 100 ; ALL-NEXT: $xmm0 = COPY [[ADD]](<4 x s32>) 101 ; ALL-NEXT: RET 0 102 %0(<4 x s32>) = IMPLICIT_DEF 103 %1(<4 x s32>) = IMPLICIT_DEF 104 %2(<4 x s32>) = G_ADD %0, %1 105 $xmm0 = COPY %2 106 RET 0 107 108... 109--- 110name: test_add_v2i64 111alignment: 16 112legalized: false 113regBankSelected: false 114registers: 115 - { id: 0, class: _ } 116 - { id: 1, class: _ } 117 - { id: 2, class: _ } 118body: | 119 bb.1 (%ir-block.0): 120 liveins: $xmm0, $xmm1 121 122 ; ALL-LABEL: name: test_add_v2i64 123 ; ALL: liveins: $xmm0, $xmm1 124 ; ALL-NEXT: {{ $}} 125 ; ALL-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF 126 ; ALL-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF 127 ; ALL-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]] 128 ; ALL-NEXT: $xmm0 = COPY [[ADD]](<2 x s64>) 129 ; ALL-NEXT: RET 0 130 %0(<2 x s64>) = IMPLICIT_DEF 131 %1(<2 x s64>) = IMPLICIT_DEF 132 %2(<2 x s64>) = G_ADD %0, %1 133 $xmm0 = COPY %2 134 RET 0 135 136... 137