1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-- -mattr=+amx-int8,avx512f -run-pass=fastpretileconfig -o - %s | FileCheck %s 3 4# Test the case which has TILELOADD being mixed in pseudo AMX instruction 5... 6--- 7name: main 8alignment: 16 9tracksRegLiveness: true 10registers: 11 - { id: 0, class: gr64_nosp } 12 - { id: 1, class: gr64 } 13 - { id: 2, class: gr16 } 14 - { id: 3, class: gr16 } 15 - { id: 4, class: tile } 16 - { id: 5, class: tile } 17 - { id: 6, class: tile } 18 - { id: 7, class: tile } 19 - { id: 8, class: gr32 } 20 - { id: 9, class: vr512 } 21frameInfo: 22 maxAlignment: 16 23stack: 24 - { id: 0, size: 1024, alignment: 16 } 25 - { id: 1, size: 64, alignment: 4 } 26machineFunctionInfo: 27 amxProgModel: ManagedRA 28body: | 29 bb.0.entry: 30 ; CHECK-LABEL: name: main 31 ; CHECK: [[AVX512_512_SET0_:%[0-9]+]]:vr512 = AVX512_512_SET0 32 ; CHECK-NEXT: VMOVUPSZmr %stack.2, 1, $noreg, 0, $noreg, [[AVX512_512_SET0_]] :: (store (s512) into %stack.2, align 4) 33 ; CHECK-NEXT: MOV8mi %stack.2, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.2, align 4) 34 ; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_nosp = MOV32ri64 32 35 ; CHECK-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg 36 ; CHECK-NEXT: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 32 37 ; CHECK-NEXT: [[MOV16ri1:%[0-9]+]]:gr16 = MOV16ri 8 38 ; CHECK-NEXT: PLDTILECFGV %stack.2, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.2, align 4) 39 ; CHECK-NEXT: $tmm0 = TILELOADD [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg 40 ; CHECK-NEXT: [[PTILELOADDV:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg 41 ; CHECK-NEXT: [[PTILELOADDV1:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg 42 ; CHECK-NEXT: [[PTILELOADDV2:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg 43 ; CHECK-NEXT: [[PTDPBSSDV:%[0-9]+]]:tile = PTDPBSSDV [[MOV16ri1]], [[MOV16ri]], [[MOV16ri]], killed [[PTILELOADDV2]], killed [[PTILELOADDV]], killed [[PTILELOADDV1]] 44 ; CHECK-NEXT: PTILESTOREDV killed [[MOV16ri1]], killed [[MOV16ri]], killed [[LEA64r]], 1, killed [[MOV32ri64_]], 0, $noreg, killed [[PTDPBSSDV]] 45 ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags 46 ; CHECK-NEXT: $eax = COPY killed [[MOV32r0_]] 47 ; CHECK-NEXT: RET 0, killed $eax 48 %0:gr64_nosp = MOV32ri64 32 49 %1:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg 50 %2:gr16 = MOV16ri 32 51 %3:gr16 = MOV16ri 8 52 $tmm0 = TILELOADD %1, 1, %0, 0, $noreg 53 %4:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg 54 %5:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg 55 %6:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg 56 %7:tile = PTDPBSSDV %3, %2, %2, killed %6, killed %4, killed %5 57 PTILESTOREDV killed %3, killed %2, killed %1, 1, killed %0, 0, $noreg, killed %7 58 %8:gr32 = MOV32r0 implicit-def dead $eflags 59 $eax = COPY killed %8 60 RET 0, killed $eax 61 62... 63# GlobalIsel doesn't use all virtual registers and there may be virtual 64# registers without a class. 65# Note that %3 doesn't have a class: gpr instead of gr64. 66--- 67name: test_unused 68legalized: true 69regBankSelected: true 70selected: true 71failedISel: false 72tracksRegLiveness: true 73registers: 74 - { id: 0, class: gr64, preferred-register: '' } 75 - { id: 1, class: gr64_with_sub_8bit, preferred-register: '' } 76 - { id: 2, class: gr64, preferred-register: '' } 77 - { id: 3, class: gpr, preferred-register: '' } 78 - { id: 4, class: gr64, preferred-register: '' } 79 - { id: 5, class: gr8, preferred-register: '' } 80liveins: 81 - { reg: '$rdi', virtual-reg: '' } 82 - { reg: '$rsi', virtual-reg: '' } 83machineFunctionInfo: 84 amxProgModel: ManagedRA 85body: | 86 bb.1.entry: 87 liveins: $rdi, $rsi 88 89 ; CHECK-LABEL: name: test_unused 90 ; CHECK: liveins: $rdi, $rsi 91 ; CHECK-NEXT: {{ $}} 92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 93 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi 94 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit 95 ; CHECK-NEXT: $cl = COPY [[COPY2]] 96 ; CHECK-NEXT: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def $eflags, implicit $cl 97 ; CHECK-NEXT: [[ADD64ri32_:%[0-9]+]]:gr64 = ADD64ri32 [[SHR64rCL]], 123456789, implicit-def $eflags 98 ; CHECK-NEXT: $rax = COPY [[ADD64ri32_]] 99 ; CHECK-NEXT: RET 0, implicit $rax 100 %0:gr64 = COPY $rdi 101 %1:gr64_with_sub_8bit = COPY $rsi 102 %5:gr8 = COPY %1.sub_8bit 103 $cl = COPY %5 104 %2:gr64 = SHR64rCL %0, implicit-def $eflags, implicit $cl 105 %4:gr64 = ADD64ri32 %2, 123456789, implicit-def $eflags 106 $rax = COPY %4 107 RET 0, implicit $rax 108 109... 110