xref: /llvm-project/llvm/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; RUN: llc -mcpu=yonah < %s
2; PR9438
3target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
4target triple = "i386-unknown-freebsd9.0"
5
6; The 'call fastcc' ties down %ebx, %ecx, and %edx.
7; A MUL8r ties down %al, leaving no GR32_ABCD registers available.
8; The coalescer can easily overallocate physical registers,
9; and register allocation fails.
10
11declare fastcc ptr @save_string(ptr %d, ptr nocapture %s) nounwind
12
13define i32 @cvtchar(ptr nocapture %sp) nounwind {
14  %temp.i = alloca [2 x i8], align 1
15  %tmp1 = load i8, ptr %sp, align 1
16  %div = udiv i8 %tmp1, 10
17  %rem = urem i8 %div, 10
18  store i8 %rem, ptr %temp.i, align 1
19  %call.i = call fastcc ptr @save_string(ptr %sp, ptr %temp.i) nounwind
20  ret i32 undef
21}
22