xref: /llvm-project/llvm/test/CodeGen/WebAssembly/simd-bitcasts.ll (revision 122b0220fd45ee71acda912b0b712bb8edb6ba46) 
1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
3
4; Test that bitcasts between vector types are lowered to zero instructions
5
6target triple = "wasm32-unknown-unknown"
7
8; CHECK-LABEL: v16i8_to_v16i8:
9; NO-SIMD128-NOT: return $0
10; SIMD128: return $0
11define <16 x i8> @v16i8_to_v16i8(<16 x i8> %v) {
12  %res = bitcast <16 x i8> %v to <16 x i8>
13  ret <16 x i8> %res
14}
15
16; CHECK-LABEL: v16i8_to_v8i16:
17; NO-SIMD128-NOT: return $0
18; SIMD128: return $0
19define <8 x i16> @v16i8_to_v8i16(<16 x i8> %v) {
20  %res = bitcast <16 x i8> %v to <8 x i16>
21  ret <8 x i16> %res
22}
23
24; CHECK-LABEL: v16i8_to_v4i32:
25; NO-SIMD128-NOT: return $0
26; SIMD128: return $0
27define <4 x i32> @v16i8_to_v4i32(<16 x i8> %v) {
28  %res = bitcast <16 x i8> %v to <4 x i32>
29  ret <4 x i32> %res
30}
31
32; CHECK-LABEL: v16i8_to_v2i64:
33; NO-SIMD128-NOT: return $0
34; SIMD128: return $0
35define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {
36  %res = bitcast <16 x i8> %v to <2 x i64>
37  ret <2 x i64> %res
38}
39
40; CHECK-LABEL: v16i8_to_v4f32:
41; NO-SIMD128-NOT: return $0
42; SIMD128: return $0
43define <4 x float> @v16i8_to_v4f32(<16 x i8> %v) {
44  %res = bitcast <16 x i8> %v to <4 x float>
45  ret <4 x float> %res
46}
47
48; CHECK-LABEL: v16i8_to_v2f64:
49; NO-SIMD128-NOT: return $0
50; SIMD128: return $0
51define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {
52  %res = bitcast <16 x i8> %v to <2 x double>
53  ret <2 x double> %res
54}
55
56; CHECK-LABEL: v8i16_to_v16i8:
57; NO-SIMD128-NOT: return $0
58; SIMD128: return $0
59define <16 x i8> @v8i16_to_v16i8(<8 x i16> %v) {
60  %res = bitcast <8 x i16> %v to <16 x i8>
61  ret <16 x i8> %res
62}
63
64; CHECK-LABEL: v8i16_to_v8i16:
65; NO-SIMD128-NOT: return $0
66; SIMD128: return $0
67define <8 x i16> @v8i16_to_v8i16(<8 x i16> %v) {
68  %res = bitcast <8 x i16> %v to <8 x i16>
69  ret <8 x i16> %res
70}
71
72; CHECK-LABEL: v8i16_to_v4i32:
73; NO-SIMD128-NOT: return $0
74; SIMD128: return $0
75define <4 x i32> @v8i16_to_v4i32(<8 x i16> %v) {
76  %res = bitcast <8 x i16> %v to <4 x i32>
77  ret <4 x i32> %res
78}
79
80; CHECK-LABEL: v8i16_to_v2i64:
81; NO-SIMD128-NOT: return $0
82; SIMD128: return $0
83define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {
84  %res = bitcast <8 x i16> %v to <2 x i64>
85  ret <2 x i64> %res
86}
87
88; CHECK-LABEL: v8i16_to_v4f32:
89; NO-SIMD128-NOT: return $0
90; SIMD128: return $0
91define <4 x float> @v8i16_to_v4f32(<8 x i16> %v) {
92  %res = bitcast <8 x i16> %v to <4 x float>
93  ret <4 x float> %res
94}
95
96; CHECK-LABEL: v8i16_to_v2f64:
97; NO-SIMD128-NOT: return $0
98; SIMD128: return $0
99define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {
100  %res = bitcast <8 x i16> %v to <2 x double>
101  ret <2 x double> %res
102}
103
104; CHECK-LABEL: v4i32_to_v16i8:
105; NO-SIMD128-NOT: return $0
106; SIMD128: return $0
107define <16 x i8> @v4i32_to_v16i8(<4 x i32> %v) {
108  %res = bitcast <4 x i32> %v to <16 x i8>
109  ret <16 x i8> %res
110}
111
112; CHECK-LABEL: v4i32_to_v8i16:
113; NO-SIMD128-NOT: return $0
114; SIMD128: return $0
115define <8 x i16> @v4i32_to_v8i16(<4 x i32> %v) {
116  %res = bitcast <4 x i32> %v to <8 x i16>
117  ret <8 x i16> %res
118}
119
120; CHECK-LABEL: v4i32_to_v4i32:
121; NO-SIMD128-NOT: return $0
122; SIMD128: return $0
123define <4 x i32> @v4i32_to_v4i32(<4 x i32> %v) {
124  %res = bitcast <4 x i32> %v to <4 x i32>
125  ret <4 x i32> %res
126}
127
128; CHECK-LABEL: v4i32_to_v2i64:
129; NO-SIMD128-NOT: return $0
130; SIMD128: return $0
131define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {
132  %res = bitcast <4 x i32> %v to <2 x i64>
133  ret <2 x i64> %res
134}
135
136; CHECK-LABEL: v4i32_to_v4f32:
137; NO-SIMD128-NOT: return $0
138; SIMD128: return $0
139define <4 x float> @v4i32_to_v4f32(<4 x i32> %v) {
140  %res = bitcast <4 x i32> %v to <4 x float>
141  ret <4 x float> %res
142}
143
144; CHECK-LABEL: v4i32_to_v2f64:
145; NO-SIMD128-NOT: return $0
146; SIMD128: return $0
147define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {
148  %res = bitcast <4 x i32> %v to <2 x double>
149  ret <2 x double> %res
150}
151
152; CHECK-LABEL: v2i64_to_v16i8:
153; NO-SIMD128-NOT: return $0
154; SIMD128: return $0
155define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {
156  %res = bitcast <2 x i64> %v to <16 x i8>
157  ret <16 x i8> %res
158}
159
160; CHECK-LABEL: v2i64_to_v8i16:
161; NO-SIMD128-NOT: return $0
162; SIMD128: return $0
163define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {
164  %res = bitcast <2 x i64> %v to <8 x i16>
165  ret <8 x i16> %res
166}
167
168; CHECK-LABEL: v2i64_to_v4i32:
169; NO-SIMD128-NOT: return $0
170; SIMD128: return $0
171define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {
172  %res = bitcast <2 x i64> %v to <4 x i32>
173  ret <4 x i32> %res
174}
175
176; CHECK-LABEL: v2i64_to_v2i64:
177; NO-SIMD128-NOT: return $0
178; SIMD128: return $0
179define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {
180  %res = bitcast <2 x i64> %v to <2 x i64>
181  ret <2 x i64> %res
182}
183
184; CHECK-LABEL: v2i64_to_v4f32:
185; NO-SIMD128-NOT: return $0
186; SIMD128: return $0
187define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {
188  %res = bitcast <2 x i64> %v to <4 x float>
189  ret <4 x float> %res
190}
191
192; CHECK-LABEL: v2i64_to_v2f64:
193; NO-SIMD128-NOT: return $0
194; SIMD128: return $0
195define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {
196  %res = bitcast <2 x i64> %v to <2 x double>
197  ret <2 x double> %res
198}
199
200; CHECK-LABEL: v4f32_to_v16i8:
201; NO-SIMD128-NOT: return $0
202; SIMD128: return $0
203define <16 x i8> @v4f32_to_v16i8(<4 x float> %v) {
204  %res = bitcast <4 x float> %v to <16 x i8>
205  ret <16 x i8> %res
206}
207
208; CHECK-LABEL: v4f32_to_v8i16:
209; NO-SIMD128-NOT: return $0
210; SIMD128: return $0
211define <8 x i16> @v4f32_to_v8i16(<4 x float> %v) {
212  %res = bitcast <4 x float> %v to <8 x i16>
213  ret <8 x i16> %res
214}
215
216; CHECK-LABEL: v4f32_to_v4i32:
217; NO-SIMD128-NOT: return $0
218; SIMD128: return $0
219define <4 x i32> @v4f32_to_v4i32(<4 x float> %v) {
220  %res = bitcast <4 x float> %v to <4 x i32>
221  ret <4 x i32> %res
222}
223
224; CHECK-LABEL: v4f32_to_v2i64:
225; NO-SIMD128-NOT: return $0
226; SIMD128: return $0
227define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {
228  %res = bitcast <4 x float> %v to <2 x i64>
229  ret <2 x i64> %res
230}
231
232; CHECK-LABEL: v4f32_to_v4f32:
233; NO-SIMD128-NOT: return $0
234; SIMD128: return $0
235define <4 x float> @v4f32_to_v4f32(<4 x float> %v) {
236  %res = bitcast <4 x float> %v to <4 x float>
237  ret <4 x float> %res
238}
239
240; CHECK-LABEL: v4f32_to_v2f64:
241; NO-SIMD128-NOT: return $0
242; SIMD128: return $0
243define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {
244  %res = bitcast <4 x float> %v to <2 x double>
245  ret <2 x double> %res
246}
247
248; CHECK-LABEL: v2f64_to_v16i8:
249; NO-SIMD128-NOT: return $0
250; SIMD128: return $0
251define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {
252  %res = bitcast <2 x double> %v to <16 x i8>
253  ret <16 x i8> %res
254}
255
256; CHECK-LABEL: v2f64_to_v8i16:
257; NO-SIMD128-NOT: return $0
258; SIMD128: return $0
259define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {
260  %res = bitcast <2 x double> %v to <8 x i16>
261  ret <8 x i16> %res
262}
263
264; CHECK-LABEL: v2f64_to_v4i32:
265; NO-SIMD128-NOT: return $0
266; SIMD128: return $0
267define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {
268  %res = bitcast <2 x double> %v to <4 x i32>
269  ret <4 x i32> %res
270}
271
272; CHECK-LABEL: v2f64_to_v2i64:
273; NO-SIMD128-NOT: return $0
274; SIMD128: return $0
275define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {
276  %res = bitcast <2 x double> %v to <2 x i64>
277  ret <2 x i64> %res
278}
279
280; CHECK-LABEL: v2f64_to_v4f32:
281; NO-SIMD128-NOT: return $0
282; SIMD128: return $0
283define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {
284  %res = bitcast <2 x double> %v to <4 x float>
285  ret <4 x float> %res
286}
287
288; CHECK-LABEL: v2f64_to_v2f64:
289; NO-SIMD128-NOT: return $0
290; SIMD128: return $0
291define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {
292  %res = bitcast <2 x double> %v to <2 x double>
293  ret <2 x double> %res
294}
295