xref: /llvm-project/llvm/test/CodeGen/WebAssembly/divrem-constant.ll (revision 122b0220fd45ee71acda912b0b712bb8edb6ba46) 
1; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
2
3; Test that integer div and rem by constant are optimized appropriately.
4
5target triple = "wasm32-unknown-unknown"
6
7; CHECK-LABEL: test_udiv_2:
8; CHECK: i32.shr_u
9define i32 @test_udiv_2(i32 %x) {
10    %t = udiv i32 %x, 2
11    ret i32 %t
12}
13
14; CHECK-LABEL: test_udiv_5:
15; CHECK: i32.div_u
16define i32 @test_udiv_5(i32 %x) {
17    %t = udiv i32 %x, 5
18    ret i32 %t
19}
20
21; CHECK-LABEL: test_sdiv_2:
22; CHECK: i32.div_s
23define i32 @test_sdiv_2(i32 %x) {
24    %t = sdiv i32 %x, 2
25    ret i32 %t
26}
27
28; CHECK-LABEL: test_sdiv_5:
29; CHECK: i32.div_s
30define i32 @test_sdiv_5(i32 %x) {
31    %t = sdiv i32 %x, 5
32    ret i32 %t
33}
34
35; CHECK-LABEL: test_urem_2:
36; CHECK: i32.and
37define i32 @test_urem_2(i32 %x) {
38    %t = urem i32 %x, 2
39    ret i32 %t
40}
41
42; CHECK-LABEL: test_urem_5:
43; CHECK: i32.rem_u
44define i32 @test_urem_5(i32 %x) {
45    %t = urem i32 %x, 5
46    ret i32 %t
47}
48
49; CHECK-LABEL: test_srem_2:
50; CHECK: i32.rem_s
51define i32 @test_srem_2(i32 %x) {
52    %t = srem i32 %x, 2
53    ret i32 %t
54}
55
56; CHECK-LABEL: test_srem_5:
57; CHECK: i32.rem_s
58define i32 @test_srem_5(i32 %x) {
59    %t = srem i32 %x, 5
60    ret i32 %t
61}
62