xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vp_strided_store.ll (revision b006b60dc993b2e0ba3e412c80709477241b6be6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
3
4declare void @llvm.experimental.vp.strided.store.v256f32.p0.i64(<256 x float> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)
5
6define fastcc void @vp_strided_store_v256f32_rrm(<256 x float> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl) {
7; CHECK-LABEL: vp_strided_store_v256f32_rrm:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    and %s2, %s2, (32)0
10; CHECK-NEXT:    lvl %s2
11; CHECK-NEXT:    vstu %v0, %s1, %s0, %vm1
12; CHECK-NEXT:    b.l.t (, %s10)
13  call void @llvm.experimental.vp.strided.store.v256f32.p0.i64(<256 x float> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)
14  ret void
15}
16
17define fastcc void @vp_strided_store_v256f32_rr(<256 x float> %val, ptr %ptr, i64 %stride, i32 %evl) {
18; CHECK-LABEL: vp_strided_store_v256f32_rr:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    and %s2, %s2, (32)0
21; CHECK-NEXT:    lvl %s2
22; CHECK-NEXT:    vstu %v0, %s1, %s0
23; CHECK-NEXT:    b.l.t (, %s10)
24  %one = insertelement <256 x i1> undef, i1 1, i32 0
25  %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer
26  call void @llvm.experimental.vp.strided.store.v256f32.p0.i64(<256 x float> %val, ptr %ptr, i64 %stride, <256 x i1> %allones, i32 %evl)
27  ret void
28}
29
30define fastcc void @vp_strided_store_v256f32_ri(<256 x float> %val, ptr %ptr, i32 %evl) {
31; CHECK-LABEL: vp_strided_store_v256f32_ri:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    and %s1, %s1, (32)0
34; CHECK-NEXT:    lvl %s1
35; CHECK-NEXT:    vstu %v0, 24, %s0
36; CHECK-NEXT:    b.l.t (, %s10)
37  %one = insertelement <256 x i1> undef, i1 1, i32 0
38  %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer
39  call void @llvm.experimental.vp.strided.store.v256f32.p0.i64(<256 x float> %val, ptr %ptr, i64 24, <256 x i1> %allones, i32 %evl)
40  ret void
41}
42
43declare void @llvm.experimental.vp.strided.store.v256i32.p0.i64(<256 x i32> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)
44
45define fastcc void @vp_strided_store_v256i32_rrm(<256 x i32> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl) {
46; CHECK-LABEL: vp_strided_store_v256i32_rrm:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    and %s2, %s2, (32)0
49; CHECK-NEXT:    lvl %s2
50; CHECK-NEXT:    vstl %v0, %s1, %s0, %vm1
51; CHECK-NEXT:    b.l.t (, %s10)
52  call void @llvm.experimental.vp.strided.store.v256i32.p0.i64(<256 x i32> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)
53  ret void
54}
55
56define fastcc void @vp_strided_store_v256i32_rr(<256 x i32> %val, ptr %ptr, i64 %stride, i32 %evl) {
57; CHECK-LABEL: vp_strided_store_v256i32_rr:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    and %s2, %s2, (32)0
60; CHECK-NEXT:    lvl %s2
61; CHECK-NEXT:    vstl %v0, %s1, %s0
62; CHECK-NEXT:    b.l.t (, %s10)
63  %one = insertelement <256 x i1> undef, i1 1, i32 0
64  %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer
65  call void @llvm.experimental.vp.strided.store.v256i32.p0.i64(<256 x i32> %val, ptr %ptr, i64 %stride, <256 x i1> %allones, i32 %evl)
66  ret void
67}
68
69define fastcc void @vp_strided_store_v256i32_ri(<256 x i32> %val, ptr %ptr, i32 %evl) {
70; CHECK-LABEL: vp_strided_store_v256i32_ri:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    and %s1, %s1, (32)0
73; CHECK-NEXT:    lvl %s1
74; CHECK-NEXT:    vstl %v0, 24, %s0
75; CHECK-NEXT:    b.l.t (, %s10)
76  %one = insertelement <256 x i1> undef, i1 1, i32 0
77  %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer
78  call void @llvm.experimental.vp.strided.store.v256i32.p0.i64(<256 x i32> %val, ptr %ptr, i64 24, <256 x i1> %allones, i32 %evl)
79  ret void
80}
81
82declare void @llvm.experimental.vp.strided.store.v256f64.p0.i64(<256 x double> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)
83
84define fastcc void @vp_strided_store_v256f64_rrm(<256 x double> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl) {
85; CHECK-LABEL: vp_strided_store_v256f64_rrm:
86; CHECK:       # %bb.0:
87; CHECK-NEXT:    and %s2, %s2, (32)0
88; CHECK-NEXT:    lvl %s2
89; CHECK-NEXT:    vst %v0, %s1, %s0, %vm1
90; CHECK-NEXT:    b.l.t (, %s10)
91  call void @llvm.experimental.vp.strided.store.v256f64.p0.i64(<256 x double> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)
92  ret void
93}
94
95define fastcc void @vp_strided_store_v256f64_rr(<256 x double> %val, ptr %ptr, i64 %stride, i32 %evl) {
96; CHECK-LABEL: vp_strided_store_v256f64_rr:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    and %s2, %s2, (32)0
99; CHECK-NEXT:    lvl %s2
100; CHECK-NEXT:    vst %v0, %s1, %s0
101; CHECK-NEXT:    b.l.t (, %s10)
102  %one = insertelement <256 x i1> undef, i1 1, i32 0
103  %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer
104  call void @llvm.experimental.vp.strided.store.v256f64.p0.i64(<256 x double> %val, ptr %ptr, i64 %stride, <256 x i1> %allones, i32 %evl)
105  ret void
106}
107
108define fastcc void @vp_strided_store_v256f64_ri(<256 x double> %val, ptr %ptr, i32 %evl) {
109; CHECK-LABEL: vp_strided_store_v256f64_ri:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    and %s1, %s1, (32)0
112; CHECK-NEXT:    lvl %s1
113; CHECK-NEXT:    vst %v0, 24, %s0
114; CHECK-NEXT:    b.l.t (, %s10)
115  %one = insertelement <256 x i1> undef, i1 1, i32 0
116  %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer
117  call void @llvm.experimental.vp.strided.store.v256f64.p0.i64(<256 x double> %val, ptr %ptr, i64 24, <256 x i1> %allones, i32 %evl)
118  ret void
119}
120
121declare void @llvm.experimental.vp.strided.store.v256i64.p0.i64(<256 x i64> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)
122
123define fastcc void @vp_strided_store_v256i64_rrm(<256 x i64> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl) {
124; CHECK-LABEL: vp_strided_store_v256i64_rrm:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    and %s2, %s2, (32)0
127; CHECK-NEXT:    lvl %s2
128; CHECK-NEXT:    vst %v0, %s1, %s0, %vm1
129; CHECK-NEXT:    b.l.t (, %s10)
130  call void @llvm.experimental.vp.strided.store.v256i64.p0.i64(<256 x i64> %val, ptr %ptr, i64 %stride, <256 x i1> %mask, i32 %evl)
131  ret void
132}
133
134define fastcc void @vp_strided_store_v256i64_rr(<256 x i64> %val, ptr %ptr, i64 %stride, i32 %evl) {
135; CHECK-LABEL: vp_strided_store_v256i64_rr:
136; CHECK:       # %bb.0:
137; CHECK-NEXT:    and %s2, %s2, (32)0
138; CHECK-NEXT:    lvl %s2
139; CHECK-NEXT:    vst %v0, %s1, %s0
140; CHECK-NEXT:    b.l.t (, %s10)
141  %one = insertelement <256 x i1> undef, i1 1, i32 0
142  %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer
143  call void @llvm.experimental.vp.strided.store.v256i64.p0.i64(<256 x i64> %val, ptr %ptr, i64 %stride, <256 x i1> %allones, i32 %evl)
144  ret void
145}
146
147define fastcc void @vp_strided_store_v256i64_ri(<256 x i64> %val, ptr %ptr, i32 %evl) {
148; CHECK-LABEL: vp_strided_store_v256i64_ri:
149; CHECK:       # %bb.0:
150; CHECK-NEXT:    and %s1, %s1, (32)0
151; CHECK-NEXT:    lvl %s1
152; CHECK-NEXT:    vst %v0, 24, %s0
153; CHECK-NEXT:    b.l.t (, %s10)
154  %one = insertelement <256 x i1> undef, i1 1, i32 0
155  %allones = shufflevector <256 x i1> %one, <256 x i1> undef, <256 x i32> zeroinitializer
156  call void @llvm.experimental.vp.strided.store.v256i64.p0.i64(<256 x i64> %val, ptr %ptr, i64 24, <256 x i1> %allones, i32 %evl)
157  ret void
158}
159