xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll (revision 5240e0b891fc4bf69d362199f70c94c28a7b9465) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
3
4declare <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
5
6define fastcc <256 x i32> @test_vp_sdiv_v256i32_vv(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
7; CHECK-LABEL: test_vp_sdiv_v256i32_vv:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    and %s0, %s0, (32)0
10; CHECK-NEXT:    lvl %s0
11; CHECK-NEXT:    vdivs.w.sx %v0, %v0, %v1, %vm1
12; CHECK-NEXT:    b.l.t (, %s10)
13  %r0 = call <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
14  ret <256 x i32> %r0
15}
16
17define fastcc <256 x i32> @test_vp_sdiv_v256i32_rv(i32 %s0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
18; CHECK-LABEL: test_vp_sdiv_v256i32_rv:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    and %s1, %s1, (32)0
21; CHECK-NEXT:    and %s0, %s0, (32)0
22; CHECK-NEXT:    lvl %s1
23; CHECK-NEXT:    vdivs.w.sx %v0, %s0, %v0, %vm1
24; CHECK-NEXT:    b.l.t (, %s10)
25  %xins = insertelement <256 x i32> undef, i32 %s0, i32 0
26  %i0 = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
27  %r0 = call <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
28  ret <256 x i32> %r0
29}
30
31define fastcc <256 x i32> @test_vp_sdiv_v256i32_vr(<256 x i32> %i0, i32 %s1, <256 x i1> %m, i32 %n) {
32; CHECK-LABEL: test_vp_sdiv_v256i32_vr:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    and %s1, %s1, (32)0
35; CHECK-NEXT:    and %s0, %s0, (32)0
36; CHECK-NEXT:    lvl %s1
37; CHECK-NEXT:    vdivs.w.sx %v0, %v0, %s0, %vm1
38; CHECK-NEXT:    b.l.t (, %s10)
39  %yins = insertelement <256 x i32> undef, i32 %s1, i32 0
40  %i1 = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
41  %r0 = call <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
42  ret <256 x i32> %r0
43}
44
45
46declare <256 x i64> @llvm.vp.sdiv.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
47
48define fastcc <256 x i64> @test_vp_int_v256i64_vv(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
49; CHECK-LABEL: test_vp_int_v256i64_vv:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    and %s0, %s0, (32)0
52; CHECK-NEXT:    lvl %s0
53; CHECK-NEXT:    vdivs.l %v0, %v0, %v1, %vm1
54; CHECK-NEXT:    b.l.t (, %s10)
55  %r0 = call <256 x i64> @llvm.vp.sdiv.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
56  ret <256 x i64> %r0
57}
58
59define fastcc <256 x i64> @test_vp_sdiv_v256i64_rv(i64 %s0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
60; CHECK-LABEL: test_vp_sdiv_v256i64_rv:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    and %s1, %s1, (32)0
63; CHECK-NEXT:    lvl %s1
64; CHECK-NEXT:    vdivs.l %v0, %s0, %v0, %vm1
65; CHECK-NEXT:    b.l.t (, %s10)
66  %xins = insertelement <256 x i64> undef, i64 %s0, i32 0
67  %i0 = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
68  %r0 = call <256 x i64> @llvm.vp.sdiv.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
69  ret <256 x i64> %r0
70}
71
72define fastcc <256 x i64> @test_vp_sdiv_v256i64_vr(<256 x i64> %i0, i64 %s1, <256 x i1> %m, i32 %n) {
73; CHECK-LABEL: test_vp_sdiv_v256i64_vr:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    and %s1, %s1, (32)0
76; CHECK-NEXT:    lvl %s1
77; CHECK-NEXT:    vdivs.l %v0, %v0, %s0, %vm1
78; CHECK-NEXT:    b.l.t (, %s10)
79  %yins = insertelement <256 x i64> undef, i64 %s1, i32 0
80  %i1 = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
81  %r0 = call <256 x i64> @llvm.vp.sdiv.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
82  ret <256 x i64> %r0
83}
84