xref: /llvm-project/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll (revision 8c2ad9e85f677546021880dc88e24f633ccacd93) 
1; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
2
3; Scalar argument passing must not change (same tests as in VE/Scalar/callee.ll below - this time with +vpu)
4
5define fastcc i32 @stack_stack_arg_i32_r9(i1 %0, i8 %1, i16 %2, i32 %3, i64 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9) {
6; CHECK-LABEL: stack_stack_arg_i32_r9:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    ldl.sx %s0, 248(, %s11)
9; CHECK-NEXT:    b.l.t (, %s10)
10  ret i32 %9
11}
12
13define fastcc i64 @stack_stack_arg_i64_r9(i1 %0, i8 %1, i16 %2, i32 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8, i64 %9) {
14; CHECK-LABEL: stack_stack_arg_i64_r9:
15; CHECK:       # %bb.0:
16; CHECK-NEXT:    ld %s0, 248(, %s11)
17; CHECK-NEXT:    b.l.t (, %s10)
18  ret i64 %9
19}
20
21define fastcc float @stack_stack_arg_f32_r9(float %p0, float %p1, float %p2, float %p3, float %p4, float %p5, float %p6, float %p7, float %s0, float %s1) {
22; CHECK-LABEL: stack_stack_arg_f32_r9:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    ldu %s0, 252(, %s11)
25; CHECK-NEXT:    b.l.t (, %s10)
26  ret float %s1
27}
28
29define fastcc i32 @stack_stack_arg_i32f32_r8(i32 %p0, float %p1, i32 %p2, float %p3, i32 %p4, float %p5, i32 %p6, float %p7, i32 %s0, float %s1) {
30; CHECK-LABEL: stack_stack_arg_i32f32_r8:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    ldl.sx %s0, 240(, %s11)
33; CHECK-NEXT:    b.l.t (, %s10)
34  ret i32 %s0
35}
36
37define fastcc float @stack_stack_arg_i32f32_r9(i32 %p0, float %p1, i32 %p2, float %p3, i32 %p4, float %p5, i32 %p6, float %p7, i32 %s0, float %s1) {
38; CHECK-LABEL: stack_stack_arg_i32f32_r9:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    ldu %s0, 252(, %s11)
41; CHECK-NEXT:    b.l.t (, %s10)
42  ret float %s1
43}
44
45; Vector argument passing (fastcc feature)
46
47; v0-to-v0 passthrough case without vreg copy.
48define fastcc <256 x i32> @vreg_arg_v256i32_r0(<256 x i32> %p0) {
49; CHECK-LABEL: vreg_arg_v256i32_r0:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    b.l.t (, %s10)
52  ret <256 x i32> %p0
53}
54
55define fastcc <256 x i32> @vreg_arg_v256i32_r1(<256 x i32> %p0, <256 x i32> %p1) {
56; CHECK-LABEL: vreg_arg_v256i32_r1:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    lea %s16, 256
59; CHECK-NEXT:    lvl %s16
60; CHECK-NEXT:    vor %v0, (0)1, %v1
61; CHECK-NEXT:    b.l.t (, %s10)
62  ret <256 x i32> %p1
63}
64
65define fastcc <256 x i32> @vreg_arg_v256i32_r2(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2) {
66; CHECK-LABEL: vreg_arg_v256i32_r2:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    lea %s16, 256
69; CHECK-NEXT:    lvl %s16
70; CHECK-NEXT:    vor %v0, (0)1, %v2
71; CHECK-NEXT:    b.l.t (, %s10)
72  ret <256 x i32> %p2
73}
74
75define fastcc <256 x i32> @vreg_arg_v256i32_r3(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3) {
76; CHECK-LABEL: vreg_arg_v256i32_r3:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    lea %s16, 256
79; CHECK-NEXT:    lvl %s16
80; CHECK-NEXT:    vor %v0, (0)1, %v3
81; CHECK-NEXT:    b.l.t (, %s10)
82  ret <256 x i32> %p3
83}
84
85define fastcc <256 x i32> @vreg_arg_v256i32_r4(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4) {
86; CHECK-LABEL: vreg_arg_v256i32_r4:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    lea %s16, 256
89; CHECK-NEXT:    lvl %s16
90; CHECK-NEXT:    vor %v0, (0)1, %v4
91; CHECK-NEXT:    b.l.t (, %s10)
92  ret <256 x i32> %p4
93}
94
95define fastcc <256 x i32> @vreg_arg_v256i32_r5(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5) {
96; CHECK-LABEL: vreg_arg_v256i32_r5:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    lea %s16, 256
99; CHECK-NEXT:    lvl %s16
100; CHECK-NEXT:    vor %v0, (0)1, %v5
101; CHECK-NEXT:    b.l.t (, %s10)
102  ret <256 x i32> %p5
103}
104
105define fastcc <256 x i32> @vreg_arg_v256i32_r6(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5, <256 x i32> %p6) {
106; CHECK-LABEL: vreg_arg_v256i32_r6:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    lea %s16, 256
109; CHECK-NEXT:    lvl %s16
110; CHECK-NEXT:    vor %v0, (0)1, %v6
111; CHECK-NEXT:    b.l.t (, %s10)
112  ret <256 x i32> %p6
113}
114
115; TODO: Uncomment test when vector loads are upstream (vreg stack passing).
116; define <256 x i32> @vreg_arg_v256i32_r7(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5, <256 x i32> %p6, <256 x i32> %p7) {
117;   ret <256 x i32> %p7
118; }
119
120; define <256 x i32> @vreg_arg_v256i32_r8(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5, <256 x i32> %p6, <256 x i32> %p7, <256 x i32> %p8) {
121;   ret <256 x i32> %p8
122; }
123
124define fastcc <256 x i1> @vreg_arg_v256i1_vm7(<256 x i1> %vm1, <256 x i1> %vm2, <256 x i1> %vm3, <256 x i1> %vm4, <256 x i1> %vm5, <256 x i1> %vm6, <256 x i1> %vm7, <256 x i1> %vm8) {
125; CHECK-LABEL: vreg_arg_v256i1_vm7:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    andm %vm1, %vm0, %vm6
128; CHECK-NEXT:    b.l.t (, %s10)
129  ret <256 x i1> %vm6
130}
131
132define fastcc <512 x i1> @vreg_arg_v512i1_vmp3(<512 x i1> %vmp1, <512 x i1> %vmp2, <512 x i1> %vmp3, <512 x i1> %vmp4) {
133; CHECK-LABEL: vreg_arg_v512i1_vmp3:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    andm %vm2, %vm0, %vm6
136; CHECK-NEXT:    andm %vm3, %vm0, %vm7
137; CHECK-NEXT:    b.l.t (, %s10)
138  ret <512 x i1> %vmp3
139}
140
141define fastcc <256 x i1> @vmp_cc_bug(<256 x i1> %vm1, <256 x i1> %vm2, <512 x i1> %vmp2, <256 x i1> %vm6) {
142; CHECK-LABEL: vmp_cc_bug:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    andm %vm1, %vm0, %vm6
145; CHECK-NEXT:    b.l.t (, %s10)
146  ret <256 x i1> %vm6
147}
148