1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3;;; Test vector sum intrinsic instructions 4;;; 5;;; Note: 6;;; We test VSUM*vl and VSUM*vml instructions. 7 8; Function Attrs: nounwind readnone 9define fastcc <256 x double> @vsumwsx_vvl(<256 x double> %0) { 10; CHECK-LABEL: vsumwsx_vvl: 11; CHECK: # %bb.0: 12; CHECK-NEXT: lea %s0, 256 13; CHECK-NEXT: lvl %s0 14; CHECK-NEXT: vsum.w.sx %v0, %v0 15; CHECK-NEXT: b.l.t (, %s10) 16 %2 = tail call fast <256 x double> @llvm.ve.vl.vsumwsx.vvl(<256 x double> %0, i32 256) 17 ret <256 x double> %2 18} 19 20; Function Attrs: nounwind readnone 21declare <256 x double> @llvm.ve.vl.vsumwsx.vvl(<256 x double>, i32) 22 23; Function Attrs: nounwind readnone 24define fastcc <256 x double> @vsumwsx_vvml(<256 x double> %0, <256 x i1> %1) { 25; CHECK-LABEL: vsumwsx_vvml: 26; CHECK: # %bb.0: 27; CHECK-NEXT: lea %s0, 256 28; CHECK-NEXT: lvl %s0 29; CHECK-NEXT: vsum.w.sx %v0, %v0, %vm1 30; CHECK-NEXT: b.l.t (, %s10) 31 %3 = tail call fast <256 x double> @llvm.ve.vl.vsumwsx.vvml(<256 x double> %0, <256 x i1> %1, i32 256) 32 ret <256 x double> %3 33} 34 35; Function Attrs: nounwind readnone 36declare <256 x double> @llvm.ve.vl.vsumwsx.vvml(<256 x double>, <256 x i1>, i32) 37 38; Function Attrs: nounwind readnone 39define fastcc <256 x double> @vsumwzx_vvl(<256 x double> %0) { 40; CHECK-LABEL: vsumwzx_vvl: 41; CHECK: # %bb.0: 42; CHECK-NEXT: lea %s0, 256 43; CHECK-NEXT: lvl %s0 44; CHECK-NEXT: vsum.w.zx %v0, %v0 45; CHECK-NEXT: b.l.t (, %s10) 46 %2 = tail call fast <256 x double> @llvm.ve.vl.vsumwzx.vvl(<256 x double> %0, i32 256) 47 ret <256 x double> %2 48} 49 50; Function Attrs: nounwind readnone 51declare <256 x double> @llvm.ve.vl.vsumwzx.vvl(<256 x double>, i32) 52 53; Function Attrs: nounwind readnone 54define fastcc <256 x double> @vsumwzx_vvml(<256 x double> %0, <256 x i1> %1) { 55; CHECK-LABEL: vsumwzx_vvml: 56; CHECK: # %bb.0: 57; CHECK-NEXT: lea %s0, 256 58; CHECK-NEXT: lvl %s0 59; CHECK-NEXT: vsum.w.zx %v0, %v0, %vm1 60; CHECK-NEXT: b.l.t (, %s10) 61 %3 = tail call fast <256 x double> @llvm.ve.vl.vsumwzx.vvml(<256 x double> %0, <256 x i1> %1, i32 256) 62 ret <256 x double> %3 63} 64 65; Function Attrs: nounwind readnone 66declare <256 x double> @llvm.ve.vl.vsumwzx.vvml(<256 x double>, <256 x i1>, i32) 67 68; Function Attrs: nounwind readnone 69define fastcc <256 x double> @vsuml_vvl(<256 x double> %0) { 70; CHECK-LABEL: vsuml_vvl: 71; CHECK: # %bb.0: 72; CHECK-NEXT: lea %s0, 256 73; CHECK-NEXT: lvl %s0 74; CHECK-NEXT: vsum.l %v0, %v0 75; CHECK-NEXT: b.l.t (, %s10) 76 %2 = tail call fast <256 x double> @llvm.ve.vl.vsuml.vvl(<256 x double> %0, i32 256) 77 ret <256 x double> %2 78} 79 80; Function Attrs: nounwind readnone 81declare <256 x double> @llvm.ve.vl.vsuml.vvl(<256 x double>, i32) 82 83; Function Attrs: nounwind readnone 84define fastcc <256 x double> @vsuml_vvml(<256 x double> %0, <256 x i1> %1) { 85; CHECK-LABEL: vsuml_vvml: 86; CHECK: # %bb.0: 87; CHECK-NEXT: lea %s0, 256 88; CHECK-NEXT: lvl %s0 89; CHECK-NEXT: vsum.l %v0, %v0, %vm1 90; CHECK-NEXT: b.l.t (, %s10) 91 %3 = tail call fast <256 x double> @llvm.ve.vl.vsuml.vvml(<256 x double> %0, <256 x i1> %1, i32 256) 92 ret <256 x double> %3 93} 94 95; Function Attrs: nounwind readnone 96declare <256 x double> @llvm.ve.vl.vsuml.vvml(<256 x double>, <256 x i1>, i32) 97