xref: /llvm-project/llvm/test/CodeGen/VE/Scalar/right_shift.ll (revision 44a4f9392546649f7d6247af1b816aa1f346dee0) 
1; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
2
3define signext i8 @func1(i8 signext %0, i8 signext %1) {
4; CHECK-LABEL: func1:
5; CHECK:       # %bb.0:
6; CHECK-NEXT:    sra.w.sx %s0, %s0, %s1
7; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
8; CHECK-NEXT:    b.l.t (, %s10)
9  %3 = sext i8 %0 to i32
10  %4 = sext i8 %1 to i32
11  %5 = ashr i32 %3, %4
12  %6 = trunc i32 %5 to i8
13  ret i8 %6
14}
15
16define signext i16 @func2(i16 signext %0, i16 signext %1) {
17; CHECK-LABEL: func2:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    sra.w.sx %s0, %s0, %s1
20; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
21; CHECK-NEXT:    b.l.t (, %s10)
22  %3 = sext i16 %0 to i32
23  %4 = sext i16 %1 to i32
24  %5 = ashr i32 %3, %4
25  %6 = trunc i32 %5 to i16
26  ret i16 %6
27}
28
29define i32 @func3(i32 %0, i32 %1) {
30; CHECK-LABEL: func3:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    sra.w.sx %s0, %s0, %s1
33; CHECK-NEXT:    b.l.t (, %s10)
34  %3 = ashr i32 %0, %1
35  ret i32 %3
36}
37
38define i64 @func4(i64 %0, i64 %1) {
39; CHECK-LABEL: func4:
40; CHECK:       # %bb.0:
41; CHECK-NEXT:    sra.l %s0, %s0, %s1
42; CHECK-NEXT:    b.l.t (, %s10)
43  %3 = ashr i64 %0, %1
44  ret i64 %3
45}
46
47define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
48; CHECK-LABEL: func7:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    and %s0, %s0, (32)0
51; CHECK-NEXT:    srl %s0, %s0, %s1
52; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
53; CHECK-NEXT:    b.l.t (, %s10)
54  %3 = zext i8 %0 to i32
55  %4 = zext i8 %1 to i32
56  %5 = lshr i32 %3, %4
57  %6 = trunc i32 %5 to i8
58  ret i8 %6
59}
60
61define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
62; CHECK-LABEL: func8:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    and %s0, %s0, (32)0
65; CHECK-NEXT:    srl %s0, %s0, %s1
66; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
67; CHECK-NEXT:    b.l.t (, %s10)
68  %3 = zext i16 %0 to i32
69  %4 = zext i16 %1 to i32
70  %5 = lshr i32 %3, %4
71  %6 = trunc i32 %5 to i16
72  ret i16 %6
73}
74
75define i32 @func9(i32 %0, i32 %1) {
76; CHECK-LABEL: func9:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    and %s0, %s0, (32)0
79; CHECK-NEXT:    srl %s0, %s0, %s1
80; CHECK-NEXT:    b.l.t (, %s10)
81  %3 = lshr i32 %0, %1
82  ret i32 %3
83}
84
85define i64 @func10(i64 %0, i64 %1) {
86; CHECK-LABEL: func10:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    srl %s0, %s0, %s1
89; CHECK-NEXT:    b.l.t (, %s10)
90  %3 = lshr i64 %0, %1
91  ret i64 %3
92}
93
94define signext i8 @func12(i8 signext %0) {
95; CHECK-LABEL: func12:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    sra.w.sx %s0, %s0, 5
98; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
99; CHECK-NEXT:    b.l.t (, %s10)
100  %2 = ashr i8 %0, 5
101  ret i8 %2
102}
103
104define signext i16 @func13(i16 signext %0) {
105; CHECK-LABEL: func13:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    sra.w.sx %s0, %s0, 5
108; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
109; CHECK-NEXT:    b.l.t (, %s10)
110  %2 = ashr i16 %0, 5
111  ret i16 %2
112}
113
114define i32 @func14(i32 %0) {
115; CHECK-LABEL: func14:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    sra.w.sx %s0, %s0, 5
118; CHECK-NEXT:    b.l.t (, %s10)
119  %2 = ashr i32 %0, 5
120  ret i32 %2
121}
122
123define i64 @func15(i64 %0) {
124; CHECK-LABEL: func15:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    sra.l %s0, %s0, 5
127; CHECK-NEXT:    b.l.t (, %s10)
128  %2 = ashr i64 %0, 5
129  ret i64 %2
130}
131
132define zeroext i8 @func17(i8 zeroext %0) {
133; CHECK-LABEL: func17:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    and %s0, %s0, (32)0
136; CHECK-NEXT:    srl %s0, %s0, 5
137; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
138; CHECK-NEXT:    b.l.t (, %s10)
139  %2 = lshr i8 %0, 5
140  ret i8 %2
141}
142
143define zeroext i16 @func18(i16 zeroext %0) {
144; CHECK-LABEL: func18:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    and %s0, %s0, (32)0
147; CHECK-NEXT:    srl %s0, %s0, 5
148; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
149; CHECK-NEXT:    b.l.t (, %s10)
150  %2 = lshr i16 %0, 5
151  ret i16 %2
152}
153
154define i32 @func19(i32 %0) {
155; CHECK-LABEL: func19:
156; CHECK:       # %bb.0:
157; CHECK-NEXT:    and %s0, %s0, (32)0
158; CHECK-NEXT:    srl %s0, %s0, 5
159; CHECK-NEXT:    b.l.t (, %s10)
160  %2 = lshr i32 %0, 5
161  ret i32 %2
162}
163
164define i64 @func20(i64 %0) {
165; CHECK-LABEL: func20:
166; CHECK:       # %bb.0:
167; CHECK-NEXT:    srl %s0, %s0, 5
168; CHECK-NEXT:    b.l.t (, %s10)
169  %2 = lshr i64 %0, 5
170  ret i64 %2
171}
172
173