xref: /llvm-project/llvm/test/CodeGen/VE/Scalar/brcond.ll (revision 61f9cb002debd4b28d9d03c603df9bd428969cb6)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=ve | FileCheck %s
3
4; Function Attrs: nounwind
5define void @brcond_then(i1 zeroext %0) {
6; CHECK-LABEL: brcond_then:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    breq.w 0, %s0, .LBB0_2
9; CHECK-NEXT:  # %bb.1:
10; CHECK-NEXT:    #APP
11; CHECK-NEXT:    nop
12; CHECK-NEXT:    #NO_APP
13; CHECK-NEXT:  .LBB0_2:
14; CHECK-NEXT:    b.l.t (, %s10)
15  br i1 %0, label %2, label %3
16
172:                                                ; preds = %1
18  tail call void asm sideeffect "nop", ""()
19  br label %3
20
213:                                                ; preds = %2, %1
22  ret void
23}
24
25; Function Attrs: nounwind
26define void @brcond_else(i1 zeroext %0) {
27; CHECK-LABEL: brcond_else:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    brne.w 0, %s0, .LBB1_2
30; CHECK-NEXT:  # %bb.1:
31; CHECK-NEXT:    #APP
32; CHECK-NEXT:    nop
33; CHECK-NEXT:    #NO_APP
34; CHECK-NEXT:  .LBB1_2:
35; CHECK-NEXT:    b.l.t (, %s10)
36  br i1 %0, label %3, label %2
37
382:                                                ; preds = %1
39  tail call void asm sideeffect "nop", ""()
40  br label %3
41
423:                                                ; preds = %2, %1
43  ret void
44}
45