1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc < %s -mtriple=ve | FileCheck %s 3 4; Function Attrs: nounwind 5define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) { 6; CHECK-LABEL: br_cc_i1_var: 7; CHECK: # %bb.0: 8; CHECK-NEXT: xor %s0, %s0, %s1 9; CHECK-NEXT: brne.w 0, %s0, .LBB0_2 10; CHECK-NEXT: # %bb.1: 11; CHECK-NEXT: #APP 12; CHECK-NEXT: nop 13; CHECK-NEXT: #NO_APP 14; CHECK-NEXT: .LBB0_2: 15; CHECK-NEXT: b.l.t (, %s10) 16 %3 = xor i1 %0, %1 17 br i1 %3, label %5, label %4 18 194: ; preds = %2 20 tail call void asm sideeffect "nop", ""() 21 br label %5 22 235: ; preds = %4, %2 24 ret void 25} 26 27; Function Attrs: nounwind 28define void @br_cc_i8_var(i8 signext %0, i8 signext %1) { 29; CHECK-LABEL: br_cc_i8_var: 30; CHECK: # %bb.0: 31; CHECK-NEXT: brne.w %s0, %s1, .LBB1_2 32; CHECK-NEXT: # %bb.1: 33; CHECK-NEXT: #APP 34; CHECK-NEXT: nop 35; CHECK-NEXT: #NO_APP 36; CHECK-NEXT: .LBB1_2: 37; CHECK-NEXT: b.l.t (, %s10) 38 %3 = icmp eq i8 %0, %1 39 br i1 %3, label %4, label %5 40 414: ; preds = %2 42 tail call void asm sideeffect "nop", ""() 43 br label %5 44 455: ; preds = %4, %2 46 ret void 47} 48 49; Function Attrs: nounwind 50define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) { 51; CHECK-LABEL: br_cc_u8_var: 52; CHECK: # %bb.0: 53; CHECK-NEXT: brne.w %s0, %s1, .LBB2_2 54; CHECK-NEXT: # %bb.1: 55; CHECK-NEXT: #APP 56; CHECK-NEXT: nop 57; CHECK-NEXT: #NO_APP 58; CHECK-NEXT: .LBB2_2: 59; CHECK-NEXT: b.l.t (, %s10) 60 %3 = icmp eq i8 %0, %1 61 br i1 %3, label %4, label %5 62 634: ; preds = %2 64 tail call void asm sideeffect "nop", ""() 65 br label %5 66 675: ; preds = %4, %2 68 ret void 69} 70 71; Function Attrs: nounwind 72define void @br_cc_i16_var(i16 signext %0, i16 signext %1) { 73; CHECK-LABEL: br_cc_i16_var: 74; CHECK: # %bb.0: 75; CHECK-NEXT: brne.w %s0, %s1, .LBB3_2 76; CHECK-NEXT: # %bb.1: 77; CHECK-NEXT: #APP 78; CHECK-NEXT: nop 79; CHECK-NEXT: #NO_APP 80; CHECK-NEXT: .LBB3_2: 81; CHECK-NEXT: b.l.t (, %s10) 82 %3 = icmp eq i16 %0, %1 83 br i1 %3, label %4, label %5 84 854: ; preds = %2 86 tail call void asm sideeffect "nop", ""() 87 br label %5 88 895: ; preds = %4, %2 90 ret void 91} 92 93; Function Attrs: nounwind 94define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) { 95; CHECK-LABEL: br_cc_u16_var: 96; CHECK: # %bb.0: 97; CHECK-NEXT: brne.w %s0, %s1, .LBB4_2 98; CHECK-NEXT: # %bb.1: 99; CHECK-NEXT: #APP 100; CHECK-NEXT: nop 101; CHECK-NEXT: #NO_APP 102; CHECK-NEXT: .LBB4_2: 103; CHECK-NEXT: b.l.t (, %s10) 104 %3 = icmp eq i16 %0, %1 105 br i1 %3, label %4, label %5 106 1074: ; preds = %2 108 tail call void asm sideeffect "nop", ""() 109 br label %5 110 1115: ; preds = %4, %2 112 ret void 113} 114 115; Function Attrs: nounwind 116define void @br_cc_i32_var(i32 signext %0, i32 signext %1) { 117; CHECK-LABEL: br_cc_i32_var: 118; CHECK: # %bb.0: 119; CHECK-NEXT: brne.w %s0, %s1, .LBB5_2 120; CHECK-NEXT: # %bb.1: 121; CHECK-NEXT: #APP 122; CHECK-NEXT: nop 123; CHECK-NEXT: #NO_APP 124; CHECK-NEXT: .LBB5_2: 125; CHECK-NEXT: b.l.t (, %s10) 126 %3 = icmp eq i32 %0, %1 127 br i1 %3, label %4, label %5 128 1294: ; preds = %2 130 tail call void asm sideeffect "nop", ""() 131 br label %5 132 1335: ; preds = %4, %2 134 ret void 135} 136 137; Function Attrs: nounwind 138define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) { 139; CHECK-LABEL: br_cc_u32_var: 140; CHECK: # %bb.0: 141; CHECK-NEXT: brne.w %s0, %s1, .LBB6_2 142; CHECK-NEXT: # %bb.1: 143; CHECK-NEXT: #APP 144; CHECK-NEXT: nop 145; CHECK-NEXT: #NO_APP 146; CHECK-NEXT: .LBB6_2: 147; CHECK-NEXT: b.l.t (, %s10) 148 %3 = icmp eq i32 %0, %1 149 br i1 %3, label %4, label %5 150 1514: ; preds = %2 152 tail call void asm sideeffect "nop", ""() 153 br label %5 154 1555: ; preds = %4, %2 156 ret void 157} 158 159; Function Attrs: nounwind 160define void @br_cc_i64_var(i64 %0, i64 %1) { 161; CHECK-LABEL: br_cc_i64_var: 162; CHECK: # %bb.0: 163; CHECK-NEXT: brne.l %s0, %s1, .LBB7_2 164; CHECK-NEXT: # %bb.1: 165; CHECK-NEXT: #APP 166; CHECK-NEXT: nop 167; CHECK-NEXT: #NO_APP 168; CHECK-NEXT: .LBB7_2: 169; CHECK-NEXT: b.l.t (, %s10) 170 %3 = icmp eq i64 %0, %1 171 br i1 %3, label %4, label %5 172 1734: ; preds = %2 174 tail call void asm sideeffect "nop", ""() 175 br label %5 176 1775: ; preds = %4, %2 178 ret void 179} 180 181; Function Attrs: nounwind 182define void @br_cc_u64_var(i64 %0, i64 %1) { 183; CHECK-LABEL: br_cc_u64_var: 184; CHECK: # %bb.0: 185; CHECK-NEXT: brne.l %s0, %s1, .LBB8_2 186; CHECK-NEXT: # %bb.1: 187; CHECK-NEXT: #APP 188; CHECK-NEXT: nop 189; CHECK-NEXT: #NO_APP 190; CHECK-NEXT: .LBB8_2: 191; CHECK-NEXT: b.l.t (, %s10) 192 %3 = icmp eq i64 %0, %1 193 br i1 %3, label %4, label %5 194 1954: ; preds = %2 196 tail call void asm sideeffect "nop", ""() 197 br label %5 198 1995: ; preds = %4, %2 200 ret void 201} 202 203; Function Attrs: nounwind 204define void @br_cc_i128_var(i128 %0, i128 %1) { 205; CHECK-LABEL: br_cc_i128_var: 206; CHECK: # %bb.0: 207; CHECK-NEXT: xor %s1, %s1, %s3 208; CHECK-NEXT: xor %s0, %s0, %s2 209; CHECK-NEXT: or %s0, %s0, %s1 210; CHECK-NEXT: brne.l 0, %s0, .LBB9_2 211; CHECK-NEXT: # %bb.1: 212; CHECK-NEXT: #APP 213; CHECK-NEXT: nop 214; CHECK-NEXT: #NO_APP 215; CHECK-NEXT: .LBB9_2: 216; CHECK-NEXT: b.l.t (, %s10) 217 %3 = icmp eq i128 %0, %1 218 br i1 %3, label %4, label %5 219 2204: ; preds = %2 221 tail call void asm sideeffect "nop", ""() 222 br label %5 223 2245: ; preds = %4, %2 225 ret void 226} 227 228; Function Attrs: nounwind 229define void @br_cc_u128_var(i128 %0, i128 %1) { 230; CHECK-LABEL: br_cc_u128_var: 231; CHECK: # %bb.0: 232; CHECK-NEXT: xor %s1, %s1, %s3 233; CHECK-NEXT: xor %s0, %s0, %s2 234; CHECK-NEXT: or %s0, %s0, %s1 235; CHECK-NEXT: brne.l 0, %s0, .LBB10_2 236; CHECK-NEXT: # %bb.1: 237; CHECK-NEXT: #APP 238; CHECK-NEXT: nop 239; CHECK-NEXT: #NO_APP 240; CHECK-NEXT: .LBB10_2: 241; CHECK-NEXT: b.l.t (, %s10) 242 %3 = icmp eq i128 %0, %1 243 br i1 %3, label %4, label %5 244 2454: ; preds = %2 246 tail call void asm sideeffect "nop", ""() 247 br label %5 248 2495: ; preds = %4, %2 250 ret void 251} 252 253; Function Attrs: nounwind 254define void @br_cc_float_var(float %0, float %1) { 255; CHECK-LABEL: br_cc_float_var: 256; CHECK: # %bb.0: 257; CHECK-NEXT: brne.s %s0, %s1, .LBB11_2 258; CHECK-NEXT: # %bb.1: 259; CHECK-NEXT: #APP 260; CHECK-NEXT: nop 261; CHECK-NEXT: #NO_APP 262; CHECK-NEXT: .LBB11_2: 263; CHECK-NEXT: b.l.t (, %s10) 264 %3 = fcmp fast oeq float %0, %1 265 br i1 %3, label %4, label %5 266 2674: ; preds = %2 268 tail call void asm sideeffect "nop", ""() 269 br label %5 270 2715: ; preds = %4, %2 272 ret void 273} 274 275; Function Attrs: nounwind 276define void @br_cc_double_var(double %0, double %1) { 277; CHECK-LABEL: br_cc_double_var: 278; CHECK: # %bb.0: 279; CHECK-NEXT: brne.d %s0, %s1, .LBB12_2 280; CHECK-NEXT: # %bb.1: 281; CHECK-NEXT: #APP 282; CHECK-NEXT: nop 283; CHECK-NEXT: #NO_APP 284; CHECK-NEXT: .LBB12_2: 285; CHECK-NEXT: b.l.t (, %s10) 286 %3 = fcmp fast oeq double %0, %1 287 br i1 %3, label %4, label %5 288 2894: ; preds = %2 290 tail call void asm sideeffect "nop", ""() 291 br label %5 292 2935: ; preds = %4, %2 294 ret void 295} 296 297; Function Attrs: nounwind 298define void @br_cc_quad_var(fp128 %0, fp128 %1) { 299; CHECK-LABEL: br_cc_quad_var: 300; CHECK: # %bb.0: 301; CHECK-NEXT: fcmp.q %s0, %s2, %s0 302; CHECK-NEXT: brne.d 0, %s0, .LBB13_2 303; CHECK-NEXT: # %bb.1: 304; CHECK-NEXT: #APP 305; CHECK-NEXT: nop 306; CHECK-NEXT: #NO_APP 307; CHECK-NEXT: .LBB13_2: 308; CHECK-NEXT: b.l.t (, %s10) 309 %3 = fcmp fast oeq fp128 %0, %1 310 br i1 %3, label %4, label %5 311 3124: ; preds = %2 313 tail call void asm sideeffect "nop", ""() 314 br label %5 315 3165: ; preds = %4, %2 317 ret void 318} 319 320; Function Attrs: nounwind 321define void @br_cc_i1_imm(i1 zeroext %0) { 322; CHECK-LABEL: br_cc_i1_imm: 323; CHECK: # %bb.0: 324; CHECK-NEXT: brne.w 0, %s0, .LBB14_2 325; CHECK-NEXT: # %bb.1: 326; CHECK-NEXT: #APP 327; CHECK-NEXT: nop 328; CHECK-NEXT: #NO_APP 329; CHECK-NEXT: .LBB14_2: 330; CHECK-NEXT: b.l.t (, %s10) 331 br i1 %0, label %3, label %2 332 3332: ; preds = %1 334 tail call void asm sideeffect "nop", ""() 335 br label %3 336 3373: ; preds = %2, %1 338 ret void 339} 340 341; Function Attrs: nounwind 342define void @br_cc_i8_imm(i8 signext %0) { 343; CHECK-LABEL: br_cc_i8_imm: 344; CHECK: # %bb.0: 345; CHECK-NEXT: brlt.w -10, %s0, .LBB15_2 346; CHECK-NEXT: # %bb.1: 347; CHECK-NEXT: #APP 348; CHECK-NEXT: nop 349; CHECK-NEXT: #NO_APP 350; CHECK-NEXT: .LBB15_2: 351; CHECK-NEXT: b.l.t (, %s10) 352 %2 = icmp slt i8 %0, -9 353 br i1 %2, label %3, label %4 354 3553: ; preds = %1 356 tail call void asm sideeffect "nop", ""() 357 br label %4 358 3594: ; preds = %3, %1 360 ret void 361} 362 363; Function Attrs: nounwind 364define void @br_cc_u8_imm(i8 zeroext %0) { 365; CHECK-LABEL: br_cc_u8_imm: 366; CHECK: # %bb.0: 367; CHECK-NEXT: cmpu.w %s0, 8, %s0 368; CHECK-NEXT: brgt.w 0, %s0, .LBB16_2 369; CHECK-NEXT: # %bb.1: 370; CHECK-NEXT: #APP 371; CHECK-NEXT: nop 372; CHECK-NEXT: #NO_APP 373; CHECK-NEXT: .LBB16_2: 374; CHECK-NEXT: b.l.t (, %s10) 375 %2 = icmp ult i8 %0, 9 376 br i1 %2, label %3, label %4 377 3783: ; preds = %1 379 tail call void asm sideeffect "nop", ""() 380 br label %4 381 3824: ; preds = %3, %1 383 ret void 384} 385 386; Function Attrs: nounwind 387define void @br_cc_i16_imm(i16 signext %0) { 388; CHECK-LABEL: br_cc_i16_imm: 389; CHECK: # %bb.0: 390; CHECK-NEXT: brlt.w 62, %s0, .LBB17_2 391; CHECK-NEXT: # %bb.1: 392; CHECK-NEXT: #APP 393; CHECK-NEXT: nop 394; CHECK-NEXT: #NO_APP 395; CHECK-NEXT: .LBB17_2: 396; CHECK-NEXT: b.l.t (, %s10) 397 %2 = icmp slt i16 %0, 63 398 br i1 %2, label %3, label %4 399 4003: ; preds = %1 401 tail call void asm sideeffect "nop", ""() 402 br label %4 403 4044: ; preds = %3, %1 405 ret void 406} 407 408; Function Attrs: nounwind 409define void @br_cc_u16_imm(i16 zeroext %0) { 410; CHECK-LABEL: br_cc_u16_imm: 411; CHECK: # %bb.0: 412; CHECK-NEXT: cmpu.w %s0, 63, %s0 413; CHECK-NEXT: brgt.w 0, %s0, .LBB18_2 414; CHECK-NEXT: # %bb.1: 415; CHECK-NEXT: #APP 416; CHECK-NEXT: nop 417; CHECK-NEXT: #NO_APP 418; CHECK-NEXT: .LBB18_2: 419; CHECK-NEXT: b.l.t (, %s10) 420 %2 = icmp ult i16 %0, 64 421 br i1 %2, label %3, label %4 422 4233: ; preds = %1 424 tail call void asm sideeffect "nop", ""() 425 br label %4 426 4274: ; preds = %3, %1 428 ret void 429} 430 431; Function Attrs: nounwind 432define void @br_cc_i32_imm(i32 signext %0) { 433; CHECK-LABEL: br_cc_i32_imm: 434; CHECK: # %bb.0: 435; CHECK-NEXT: brlt.w 63, %s0, .LBB19_2 436; CHECK-NEXT: # %bb.1: 437; CHECK-NEXT: #APP 438; CHECK-NEXT: nop 439; CHECK-NEXT: #NO_APP 440; CHECK-NEXT: .LBB19_2: 441; CHECK-NEXT: b.l.t (, %s10) 442 %2 = icmp slt i32 %0, 64 443 br i1 %2, label %3, label %4 444 4453: ; preds = %1 446 tail call void asm sideeffect "nop", ""() 447 br label %4 448 4494: ; preds = %3, %1 450 ret void 451} 452 453; Function Attrs: nounwind 454define void @br_cc_u32_imm(i32 zeroext %0) { 455; CHECK-LABEL: br_cc_u32_imm: 456; CHECK: # %bb.0: 457; CHECK-NEXT: cmpu.w %s0, 63, %s0 458; CHECK-NEXT: brgt.w 0, %s0, .LBB20_2 459; CHECK-NEXT: # %bb.1: 460; CHECK-NEXT: #APP 461; CHECK-NEXT: nop 462; CHECK-NEXT: #NO_APP 463; CHECK-NEXT: .LBB20_2: 464; CHECK-NEXT: b.l.t (, %s10) 465 %2 = icmp ult i32 %0, 64 466 br i1 %2, label %3, label %4 467 4683: ; preds = %1 469 tail call void asm sideeffect "nop", ""() 470 br label %4 471 4724: ; preds = %3, %1 473 ret void 474} 475 476; Function Attrs: nounwind 477define void @br_cc_i64_imm(i64 %0) { 478; CHECK-LABEL: br_cc_i64_imm: 479; CHECK: # %bb.0: 480; CHECK-NEXT: brlt.l 63, %s0, .LBB21_2 481; CHECK-NEXT: # %bb.1: 482; CHECK-NEXT: #APP 483; CHECK-NEXT: nop 484; CHECK-NEXT: #NO_APP 485; CHECK-NEXT: .LBB21_2: 486; CHECK-NEXT: b.l.t (, %s10) 487 %2 = icmp slt i64 %0, 64 488 br i1 %2, label %3, label %4 489 4903: ; preds = %1 491 tail call void asm sideeffect "nop", ""() 492 br label %4 493 4944: ; preds = %3, %1 495 ret void 496} 497 498; Function Attrs: nounwind 499define void @br_cc_u64_imm(i64 %0) { 500; CHECK-LABEL: br_cc_u64_imm: 501; CHECK: # %bb.0: 502; CHECK-NEXT: cmpu.l %s0, 63, %s0 503; CHECK-NEXT: brgt.l 0, %s0, .LBB22_2 504; CHECK-NEXT: # %bb.1: 505; CHECK-NEXT: #APP 506; CHECK-NEXT: nop 507; CHECK-NEXT: #NO_APP 508; CHECK-NEXT: .LBB22_2: 509; CHECK-NEXT: b.l.t (, %s10) 510 %2 = icmp ult i64 %0, 64 511 br i1 %2, label %3, label %4 512 5133: ; preds = %1 514 tail call void asm sideeffect "nop", ""() 515 br label %4 516 5174: ; preds = %3, %1 518 ret void 519} 520 521; Function Attrs: nounwind 522define void @br_cc_i128_imm(i128 %0) { 523; CHECK-LABEL: br_cc_i128_imm: 524; CHECK: # %bb.0: 525; CHECK-NEXT: or %s2, 0, (0)1 526; CHECK-NEXT: cmps.l %s3, %s1, (0)1 527; CHECK-NEXT: or %s4, 0, (0)1 528; CHECK-NEXT: cmov.l.gt %s4, (63)0, %s3 529; CHECK-NEXT: cmpu.l %s0, %s0, (58)0 530; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 531; CHECK-NEXT: cmov.l.eq %s4, %s2, %s1 532; CHECK-NEXT: brne.w 0, %s4, .LBB23_2 533; CHECK-NEXT: # %bb.1: 534; CHECK-NEXT: #APP 535; CHECK-NEXT: nop 536; CHECK-NEXT: #NO_APP 537; CHECK-NEXT: .LBB23_2: 538; CHECK-NEXT: b.l.t (, %s10) 539 %2 = icmp slt i128 %0, 64 540 br i1 %2, label %3, label %4 541 5423: ; preds = %1 543 tail call void asm sideeffect "nop", ""() 544 br label %4 545 5464: ; preds = %3, %1 547 ret void 548} 549 550; Function Attrs: nounwind 551define void @br_cc_u128_imm(i128 %0) { 552; CHECK-LABEL: br_cc_u128_imm: 553; CHECK: # %bb.0: 554; CHECK-NEXT: or %s2, 0, (0)1 555; CHECK-NEXT: cmps.l %s3, %s1, (0)1 556; CHECK-NEXT: or %s4, 0, (0)1 557; CHECK-NEXT: cmov.l.ne %s4, (63)0, %s3 558; CHECK-NEXT: cmpu.l %s0, %s0, (58)0 559; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0 560; CHECK-NEXT: cmov.l.eq %s4, %s2, %s1 561; CHECK-NEXT: brne.w 0, %s4, .LBB24_2 562; CHECK-NEXT: # %bb.1: 563; CHECK-NEXT: #APP 564; CHECK-NEXT: nop 565; CHECK-NEXT: #NO_APP 566; CHECK-NEXT: .LBB24_2: 567; CHECK-NEXT: b.l.t (, %s10) 568 %2 = icmp ult i128 %0, 64 569 br i1 %2, label %3, label %4 570 5713: ; preds = %1 572 tail call void asm sideeffect "nop", ""() 573 br label %4 574 5754: ; preds = %3, %1 576 ret void 577} 578 579; Function Attrs: nounwind 580define void @br_cc_float_imm(float %0) { 581; CHECK-LABEL: br_cc_float_imm: 582; CHECK: # %bb.0: 583; CHECK-NEXT: brle.s 0, %s0, .LBB25_2 584; CHECK-NEXT: # %bb.1: 585; CHECK-NEXT: #APP 586; CHECK-NEXT: nop 587; CHECK-NEXT: #NO_APP 588; CHECK-NEXT: .LBB25_2: 589; CHECK-NEXT: b.l.t (, %s10) 590 %2 = fcmp fast olt float %0, 0.000000e+00 591 br i1 %2, label %3, label %4 592 5933: ; preds = %1 594 tail call void asm sideeffect "nop", ""() 595 br label %4 596 5974: ; preds = %3, %1 598 ret void 599} 600 601; Function Attrs: nounwind 602define void @br_cc_double_imm(double %0) { 603; CHECK-LABEL: br_cc_double_imm: 604; CHECK: # %bb.0: 605; CHECK-NEXT: brle.d 0, %s0, .LBB26_2 606; CHECK-NEXT: # %bb.1: 607; CHECK-NEXT: #APP 608; CHECK-NEXT: nop 609; CHECK-NEXT: #NO_APP 610; CHECK-NEXT: .LBB26_2: 611; CHECK-NEXT: b.l.t (, %s10) 612 %2 = fcmp fast olt double %0, 0.000000e+00 613 br i1 %2, label %3, label %4 614 6153: ; preds = %1 616 tail call void asm sideeffect "nop", ""() 617 br label %4 618 6194: ; preds = %3, %1 620 ret void 621} 622 623; Function Attrs: nounwind 624define void @br_cc_quad_imm(fp128 %0) { 625; CHECK-LABEL: br_cc_quad_imm: 626; CHECK: # %bb.0: 627; CHECK-NEXT: lea %s2, .LCPI27_0@lo 628; CHECK-NEXT: and %s2, %s2, (32)0 629; CHECK-NEXT: lea.sl %s2, .LCPI27_0@hi(, %s2) 630; CHECK-NEXT: ld %s4, 8(, %s2) 631; CHECK-NEXT: ld %s5, (, %s2) 632; CHECK-NEXT: fcmp.q %s0, %s4, %s0 633; CHECK-NEXT: brge.d 0, %s0, .LBB27_2 634; CHECK-NEXT: # %bb.1: 635; CHECK-NEXT: #APP 636; CHECK-NEXT: nop 637; CHECK-NEXT: #NO_APP 638; CHECK-NEXT: .LBB27_2: 639; CHECK-NEXT: b.l.t (, %s10) 640 %2 = fcmp fast olt fp128 %0, 0xL00000000000000000000000000000000 641 br i1 %2, label %3, label %4 642 6433: ; preds = %1 644 tail call void asm sideeffect "nop", ""() 645 br label %4 646 6474: ; preds = %3, %1 648 ret void 649} 650 651; Function Attrs: nounwind 652define void @br_cc_imm_i1(i1 zeroext %0) { 653; CHECK-LABEL: br_cc_imm_i1: 654; CHECK: # %bb.0: 655; CHECK-NEXT: breq.w 0, %s0, .LBB28_2 656; CHECK-NEXT: # %bb.1: 657; CHECK-NEXT: #APP 658; CHECK-NEXT: nop 659; CHECK-NEXT: #NO_APP 660; CHECK-NEXT: .LBB28_2: 661; CHECK-NEXT: b.l.t (, %s10) 662 br i1 %0, label %2, label %3 663 6642: ; preds = %1 665 tail call void asm sideeffect "nop", ""() 666 br label %3 667 6683: ; preds = %2, %1 669 ret void 670} 671 672; Function Attrs: nounwind 673define void @br_cc_imm_i8(i8 signext %0) { 674; CHECK-LABEL: br_cc_imm_i8: 675; CHECK: # %bb.0: 676; CHECK-NEXT: brgt.w -9, %s0, .LBB29_2 677; CHECK-NEXT: # %bb.1: 678; CHECK-NEXT: #APP 679; CHECK-NEXT: nop 680; CHECK-NEXT: #NO_APP 681; CHECK-NEXT: .LBB29_2: 682; CHECK-NEXT: b.l.t (, %s10) 683 %2 = icmp sgt i8 %0, -10 684 br i1 %2, label %3, label %4 685 6863: ; preds = %1 687 tail call void asm sideeffect "nop", ""() 688 br label %4 689 6904: ; preds = %3, %1 691 ret void 692} 693 694; Function Attrs: nounwind 695define void @br_cc_imm_u8(i8 zeroext %0) { 696; CHECK-LABEL: br_cc_imm_u8: 697; CHECK: # %bb.0: 698; CHECK-NEXT: cmpu.w %s0, 9, %s0 699; CHECK-NEXT: brlt.w 0, %s0, .LBB30_2 700; CHECK-NEXT: # %bb.1: 701; CHECK-NEXT: #APP 702; CHECK-NEXT: nop 703; CHECK-NEXT: #NO_APP 704; CHECK-NEXT: .LBB30_2: 705; CHECK-NEXT: b.l.t (, %s10) 706 %2 = icmp ugt i8 %0, 8 707 br i1 %2, label %3, label %4 708 7093: ; preds = %1 710 tail call void asm sideeffect "nop", ""() 711 br label %4 712 7134: ; preds = %3, %1 714 ret void 715} 716 717; Function Attrs: nounwind 718define void @br_cc_imm_i16(i16 signext %0) { 719; CHECK-LABEL: br_cc_imm_i16: 720; CHECK: # %bb.0: 721; CHECK-NEXT: brgt.w 63, %s0, .LBB31_2 722; CHECK-NEXT: # %bb.1: 723; CHECK-NEXT: #APP 724; CHECK-NEXT: nop 725; CHECK-NEXT: #NO_APP 726; CHECK-NEXT: .LBB31_2: 727; CHECK-NEXT: b.l.t (, %s10) 728 %2 = icmp sgt i16 %0, 62 729 br i1 %2, label %3, label %4 730 7313: ; preds = %1 732 tail call void asm sideeffect "nop", ""() 733 br label %4 734 7354: ; preds = %3, %1 736 ret void 737} 738 739; Function Attrs: nounwind 740define void @br_cc_imm_u16(i16 zeroext %0) { 741; CHECK-LABEL: br_cc_imm_u16: 742; CHECK: # %bb.0: 743; CHECK-NEXT: lea %s1, 64 744; CHECK-NEXT: cmpu.w %s0, %s1, %s0 745; CHECK-NEXT: brlt.w 0, %s0, .LBB32_2 746; CHECK-NEXT: # %bb.1: 747; CHECK-NEXT: #APP 748; CHECK-NEXT: nop 749; CHECK-NEXT: #NO_APP 750; CHECK-NEXT: .LBB32_2: 751; CHECK-NEXT: b.l.t (, %s10) 752 %2 = icmp ugt i16 %0, 63 753 br i1 %2, label %3, label %4 754 7553: ; preds = %1 756 tail call void asm sideeffect "nop", ""() 757 br label %4 758 7594: ; preds = %3, %1 760 ret void 761} 762 763; Function Attrs: nounwind 764define void @br_cc_imm_i32(i32 signext %0) { 765; CHECK-LABEL: br_cc_imm_i32: 766; CHECK: # %bb.0: 767; CHECK-NEXT: brgt.w -64, %s0, .LBB33_2 768; CHECK-NEXT: # %bb.1: 769; CHECK-NEXT: #APP 770; CHECK-NEXT: nop 771; CHECK-NEXT: #NO_APP 772; CHECK-NEXT: .LBB33_2: 773; CHECK-NEXT: b.l.t (, %s10) 774 %2 = icmp sgt i32 %0, -65 775 br i1 %2, label %3, label %4 776 7773: ; preds = %1 778 tail call void asm sideeffect "nop", ""() 779 br label %4 780 7814: ; preds = %3, %1 782 ret void 783} 784 785; Function Attrs: nounwind 786define void @br_cc_imm_u32(i32 zeroext %0) { 787; CHECK-LABEL: br_cc_imm_u32: 788; CHECK: # %bb.0: 789; CHECK-NEXT: cmpu.w %s0, -64, %s0 790; CHECK-NEXT: brlt.w 0, %s0, .LBB34_2 791; CHECK-NEXT: # %bb.1: 792; CHECK-NEXT: #APP 793; CHECK-NEXT: nop 794; CHECK-NEXT: #NO_APP 795; CHECK-NEXT: .LBB34_2: 796; CHECK-NEXT: b.l.t (, %s10) 797 %2 = icmp ugt i32 %0, -65 798 br i1 %2, label %3, label %4 799 8003: ; preds = %1 801 tail call void asm sideeffect "nop", ""() 802 br label %4 803 8044: ; preds = %3, %1 805 ret void 806} 807 808; Function Attrs: nounwind 809define void @br_cc_imm_i64(i64 %0) { 810; CHECK-LABEL: br_cc_imm_i64: 811; CHECK: # %bb.0: 812; CHECK-NEXT: brgt.l -64, %s0, .LBB35_2 813; CHECK-NEXT: # %bb.1: 814; CHECK-NEXT: #APP 815; CHECK-NEXT: nop 816; CHECK-NEXT: #NO_APP 817; CHECK-NEXT: .LBB35_2: 818; CHECK-NEXT: b.l.t (, %s10) 819 %2 = icmp sgt i64 %0, -65 820 br i1 %2, label %3, label %4 821 8223: ; preds = %1 823 tail call void asm sideeffect "nop", ""() 824 br label %4 825 8264: ; preds = %3, %1 827 ret void 828} 829 830; Function Attrs: nounwind 831define void @br_cc_imm_u64(i64 %0) { 832; CHECK-LABEL: br_cc_imm_u64: 833; CHECK: # %bb.0: 834; CHECK-NEXT: cmpu.l %s0, -64, %s0 835; CHECK-NEXT: brlt.l 0, %s0, .LBB36_2 836; CHECK-NEXT: # %bb.1: 837; CHECK-NEXT: #APP 838; CHECK-NEXT: nop 839; CHECK-NEXT: #NO_APP 840; CHECK-NEXT: .LBB36_2: 841; CHECK-NEXT: b.l.t (, %s10) 842 %2 = icmp ugt i64 %0, -65 843 br i1 %2, label %3, label %4 844 8453: ; preds = %1 846 tail call void asm sideeffect "nop", ""() 847 br label %4 848 8494: ; preds = %3, %1 850 ret void 851} 852 853; Function Attrs: nounwind 854define void @br_cc_imm_i128(i128 %0) { 855; CHECK-LABEL: br_cc_imm_i128: 856; CHECK: # %bb.0: 857; CHECK-NEXT: cmps.l %s2, %s1, (0)0 858; CHECK-NEXT: or %s3, 0, (0)1 859; CHECK-NEXT: or %s4, 0, (0)1 860; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s2 861; CHECK-NEXT: cmpu.l %s0, %s0, (58)1 862; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 863; CHECK-NEXT: cmpu.l %s0, %s1, (0)0 864; CHECK-NEXT: cmov.l.eq %s4, %s3, %s0 865; CHECK-NEXT: brne.w 0, %s4, .LBB37_2 866; CHECK-NEXT: # %bb.1: 867; CHECK-NEXT: #APP 868; CHECK-NEXT: nop 869; CHECK-NEXT: #NO_APP 870; CHECK-NEXT: .LBB37_2: 871; CHECK-NEXT: b.l.t (, %s10) 872 %2 = icmp sgt i128 %0, -65 873 br i1 %2, label %3, label %4 874 8753: ; preds = %1 876 tail call void asm sideeffect "nop", ""() 877 br label %4 878 8794: ; preds = %3, %1 880 ret void 881} 882 883; Function Attrs: nounwind 884define void @br_cc_imm_u128(i128 %0) { 885; CHECK-LABEL: br_cc_imm_u128: 886; CHECK: # %bb.0: 887; CHECK-NEXT: cmps.l %s2, %s1, (0)0 888; CHECK-NEXT: or %s3, 0, (0)1 889; CHECK-NEXT: or %s4, 0, (0)1 890; CHECK-NEXT: cmov.l.ne %s4, (63)0, %s2 891; CHECK-NEXT: cmpu.l %s0, %s0, (58)1 892; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0 893; CHECK-NEXT: cmpu.l %s0, %s1, (0)0 894; CHECK-NEXT: cmov.l.eq %s4, %s3, %s0 895; CHECK-NEXT: brne.w 0, %s4, .LBB38_2 896; CHECK-NEXT: # %bb.1: 897; CHECK-NEXT: #APP 898; CHECK-NEXT: nop 899; CHECK-NEXT: #NO_APP 900; CHECK-NEXT: .LBB38_2: 901; CHECK-NEXT: b.l.t (, %s10) 902 %2 = icmp ugt i128 %0, -65 903 br i1 %2, label %3, label %4 904 9053: ; preds = %1 906 tail call void asm sideeffect "nop", ""() 907 br label %4 908 9094: ; preds = %3, %1 910 ret void 911} 912 913; Function Attrs: nounwind 914define void @br_cc_imm_float(float %0) { 915; CHECK-LABEL: br_cc_imm_float: 916; CHECK: # %bb.0: 917; CHECK-NEXT: brgt.s 0, %s0, .LBB39_2 918; CHECK-NEXT: # %bb.1: 919; CHECK-NEXT: #APP 920; CHECK-NEXT: nop 921; CHECK-NEXT: #NO_APP 922; CHECK-NEXT: .LBB39_2: 923; CHECK-NEXT: b.l.t (, %s10) 924 %2 = fcmp fast ult float %0, 0.000000e+00 925 br i1 %2, label %4, label %3 926 9273: ; preds = %1 928 tail call void asm sideeffect "nop", ""() 929 br label %4 930 9314: ; preds = %3, %1 932 ret void 933} 934 935; Function Attrs: nounwind 936define void @br_cc_imm_double(double %0) { 937; CHECK-LABEL: br_cc_imm_double: 938; CHECK: # %bb.0: 939; CHECK-NEXT: brgt.d 0, %s0, .LBB40_2 940; CHECK-NEXT: # %bb.1: 941; CHECK-NEXT: #APP 942; CHECK-NEXT: nop 943; CHECK-NEXT: #NO_APP 944; CHECK-NEXT: .LBB40_2: 945; CHECK-NEXT: b.l.t (, %s10) 946 %2 = fcmp fast ult double %0, 0.000000e+00 947 br i1 %2, label %4, label %3 948 9493: ; preds = %1 950 tail call void asm sideeffect "nop", ""() 951 br label %4 952 9534: ; preds = %3, %1 954 ret void 955} 956 957; Function Attrs: nounwind 958define void @br_cc_imm_quad(fp128 %0) { 959; CHECK-LABEL: br_cc_imm_quad: 960; CHECK: # %bb.0: 961; CHECK-NEXT: lea %s2, .LCPI41_0@lo 962; CHECK-NEXT: and %s2, %s2, (32)0 963; CHECK-NEXT: lea.sl %s2, .LCPI41_0@hi(, %s2) 964; CHECK-NEXT: ld %s4, 8(, %s2) 965; CHECK-NEXT: ld %s5, (, %s2) 966; CHECK-NEXT: fcmp.q %s0, %s4, %s0 967; CHECK-NEXT: brlt.d 0, %s0, .LBB41_2 968; CHECK-NEXT: # %bb.1: 969; CHECK-NEXT: #APP 970; CHECK-NEXT: nop 971; CHECK-NEXT: #NO_APP 972; CHECK-NEXT: .LBB41_2: 973; CHECK-NEXT: b.l.t (, %s10) 974 %2 = fcmp fast ult fp128 %0, 0xL00000000000000000000000000000000 975 br i1 %2, label %4, label %3 976 9773: ; preds = %1 978 tail call void asm sideeffect "nop", ""() 979 br label %4 980 9814: ; preds = %3, %1 982 ret void 983} 984