1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc < %s -mtriple=ve | FileCheck %s 3 4;;; Test atomic swap for all types and all memory order 5;;; 6;;; Note: 7;;; - We test i1/i8/i16/i32/i64/i128/u8/u16/u32/u64/u128. 8;;; - We test relaxed, acquire, and seq_cst. 9;;; - We test only exchange with variables since VE doesn't have exchange 10;;; instructions with immediate values. 11;;; - We test against an object, a stack object, and a global variable. 12 13%"struct.std::__1::atomic" = type { %"struct.std::__1::__atomic_base" } 14%"struct.std::__1::__atomic_base" = type { %"struct.std::__1::__cxx_atomic_impl" } 15%"struct.std::__1::__cxx_atomic_impl" = type { %"struct.std::__1::__cxx_atomic_base_impl" } 16%"struct.std::__1::__cxx_atomic_base_impl" = type { i8 } 17%"struct.std::__1::atomic.0" = type { %"struct.std::__1::__atomic_base.1" } 18%"struct.std::__1::__atomic_base.1" = type { %"struct.std::__1::__atomic_base.2" } 19%"struct.std::__1::__atomic_base.2" = type { %"struct.std::__1::__cxx_atomic_impl.3" } 20%"struct.std::__1::__cxx_atomic_impl.3" = type { %"struct.std::__1::__cxx_atomic_base_impl.4" } 21%"struct.std::__1::__cxx_atomic_base_impl.4" = type { i8 } 22%"struct.std::__1::atomic.5" = type { %"struct.std::__1::__atomic_base.6" } 23%"struct.std::__1::__atomic_base.6" = type { %"struct.std::__1::__atomic_base.7" } 24%"struct.std::__1::__atomic_base.7" = type { %"struct.std::__1::__cxx_atomic_impl.8" } 25%"struct.std::__1::__cxx_atomic_impl.8" = type { %"struct.std::__1::__cxx_atomic_base_impl.9" } 26%"struct.std::__1::__cxx_atomic_base_impl.9" = type { i8 } 27%"struct.std::__1::atomic.10" = type { %"struct.std::__1::__atomic_base.11" } 28%"struct.std::__1::__atomic_base.11" = type { %"struct.std::__1::__atomic_base.12" } 29%"struct.std::__1::__atomic_base.12" = type { %"struct.std::__1::__cxx_atomic_impl.13" } 30%"struct.std::__1::__cxx_atomic_impl.13" = type { %"struct.std::__1::__cxx_atomic_base_impl.14" } 31%"struct.std::__1::__cxx_atomic_base_impl.14" = type { i16 } 32%"struct.std::__1::atomic.15" = type { %"struct.std::__1::__atomic_base.16" } 33%"struct.std::__1::__atomic_base.16" = type { %"struct.std::__1::__atomic_base.17" } 34%"struct.std::__1::__atomic_base.17" = type { %"struct.std::__1::__cxx_atomic_impl.18" } 35%"struct.std::__1::__cxx_atomic_impl.18" = type { %"struct.std::__1::__cxx_atomic_base_impl.19" } 36%"struct.std::__1::__cxx_atomic_base_impl.19" = type { i16 } 37%"struct.std::__1::atomic.20" = type { %"struct.std::__1::__atomic_base.21" } 38%"struct.std::__1::__atomic_base.21" = type { %"struct.std::__1::__atomic_base.22" } 39%"struct.std::__1::__atomic_base.22" = type { %"struct.std::__1::__cxx_atomic_impl.23" } 40%"struct.std::__1::__cxx_atomic_impl.23" = type { %"struct.std::__1::__cxx_atomic_base_impl.24" } 41%"struct.std::__1::__cxx_atomic_base_impl.24" = type { i32 } 42%"struct.std::__1::atomic.25" = type { %"struct.std::__1::__atomic_base.26" } 43%"struct.std::__1::__atomic_base.26" = type { %"struct.std::__1::__atomic_base.27" } 44%"struct.std::__1::__atomic_base.27" = type { %"struct.std::__1::__cxx_atomic_impl.28" } 45%"struct.std::__1::__cxx_atomic_impl.28" = type { %"struct.std::__1::__cxx_atomic_base_impl.29" } 46%"struct.std::__1::__cxx_atomic_base_impl.29" = type { i32 } 47%"struct.std::__1::atomic.30" = type { %"struct.std::__1::__atomic_base.31" } 48%"struct.std::__1::__atomic_base.31" = type { %"struct.std::__1::__atomic_base.32" } 49%"struct.std::__1::__atomic_base.32" = type { %"struct.std::__1::__cxx_atomic_impl.33" } 50%"struct.std::__1::__cxx_atomic_impl.33" = type { %"struct.std::__1::__cxx_atomic_base_impl.34" } 51%"struct.std::__1::__cxx_atomic_base_impl.34" = type { i64 } 52%"struct.std::__1::atomic.35" = type { %"struct.std::__1::__atomic_base.36" } 53%"struct.std::__1::__atomic_base.36" = type { %"struct.std::__1::__atomic_base.37" } 54%"struct.std::__1::__atomic_base.37" = type { %"struct.std::__1::__cxx_atomic_impl.38" } 55%"struct.std::__1::__cxx_atomic_impl.38" = type { %"struct.std::__1::__cxx_atomic_base_impl.39" } 56%"struct.std::__1::__cxx_atomic_base_impl.39" = type { i64 } 57%"struct.std::__1::atomic.40" = type { %"struct.std::__1::__atomic_base.41" } 58%"struct.std::__1::__atomic_base.41" = type { %"struct.std::__1::__atomic_base.42" } 59%"struct.std::__1::__atomic_base.42" = type { %"struct.std::__1::__cxx_atomic_impl.43" } 60%"struct.std::__1::__cxx_atomic_impl.43" = type { %"struct.std::__1::__cxx_atomic_base_impl.44" } 61%"struct.std::__1::__cxx_atomic_base_impl.44" = type { i128 } 62%"struct.std::__1::atomic.45" = type { %"struct.std::__1::__atomic_base.46" } 63%"struct.std::__1::__atomic_base.46" = type { %"struct.std::__1::__atomic_base.47" } 64%"struct.std::__1::__atomic_base.47" = type { %"struct.std::__1::__cxx_atomic_impl.48" } 65%"struct.std::__1::__cxx_atomic_impl.48" = type { %"struct.std::__1::__cxx_atomic_base_impl.49" } 66%"struct.std::__1::__cxx_atomic_base_impl.49" = type { i128 } 67 68@gv_i1 = global %"struct.std::__1::atomic" zeroinitializer, align 4 69@gv_i8 = global %"struct.std::__1::atomic.0" zeroinitializer, align 4 70@gv_u8 = global %"struct.std::__1::atomic.5" zeroinitializer, align 4 71@gv_i16 = global %"struct.std::__1::atomic.10" zeroinitializer, align 4 72@gv_u16 = global %"struct.std::__1::atomic.15" zeroinitializer, align 4 73@gv_i32 = global %"struct.std::__1::atomic.20" zeroinitializer, align 4 74@gv_u32 = global %"struct.std::__1::atomic.25" zeroinitializer, align 4 75@gv_i64 = global %"struct.std::__1::atomic.30" zeroinitializer, align 8 76@gv_u64 = global %"struct.std::__1::atomic.35" zeroinitializer, align 8 77@gv_i128 = global %"struct.std::__1::atomic.40" zeroinitializer, align 16 78@gv_u128 = global %"struct.std::__1::atomic.45" zeroinitializer, align 16 79 80; Function Attrs: nofree norecurse nounwind mustprogress 81define zeroext i1 @_Z22atomic_swap_relaxed_i1RNSt3__16atomicIbEEb(ptr nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { 82; CHECK-LABEL: _Z22atomic_swap_relaxed_i1RNSt3__16atomicIbEEb: 83; CHECK: # %bb.0: 84; CHECK-NEXT: and %s2, 3, %s0 85; CHECK-NEXT: sla.w.sx %s3, %s2, 3 86; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 87; CHECK-NEXT: and %s0, -4, %s0 88; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 89; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 90; CHECK-NEXT: and %s0, %s1, (32)0 91; CHECK-NEXT: srl %s0, %s0, %s3 92; CHECK-NEXT: and %s0, 1, %s0 93; CHECK-NEXT: b.l.t (, %s10) 94 %3 = zext i1 %1 to i8 95 %4 = atomicrmw xchg ptr %0, i8 %3 monotonic 96 %5 = and i8 %4, 1 97 %6 = icmp ne i8 %5, 0 98 ret i1 %6 99} 100 101; Function Attrs: nofree norecurse nounwind mustprogress 102define signext i8 @_Z22atomic_swap_relaxed_i8RNSt3__16atomicIcEEc(ptr nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { 103; CHECK-LABEL: _Z22atomic_swap_relaxed_i8RNSt3__16atomicIcEEc: 104; CHECK: # %bb.0: 105; CHECK-NEXT: and %s2, 3, %s0 106; CHECK-NEXT: sla.w.sx %s3, %s2, 3 107; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 108; CHECK-NEXT: and %s0, -4, %s0 109; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 110; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 111; CHECK-NEXT: and %s0, %s1, (32)0 112; CHECK-NEXT: srl %s0, %s0, %s3 113; CHECK-NEXT: sll %s0, %s0, 56 114; CHECK-NEXT: sra.l %s0, %s0, 56 115; CHECK-NEXT: b.l.t (, %s10) 116 %3 = atomicrmw xchg ptr %0, i8 %1 monotonic 117 ret i8 %3 118} 119 120; Function Attrs: nofree norecurse nounwind mustprogress 121define zeroext i8 @_Z22atomic_swap_relaxed_u8RNSt3__16atomicIhEEh(ptr nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { 122; CHECK-LABEL: _Z22atomic_swap_relaxed_u8RNSt3__16atomicIhEEh: 123; CHECK: # %bb.0: 124; CHECK-NEXT: and %s2, 3, %s0 125; CHECK-NEXT: sla.w.sx %s3, %s2, 3 126; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 127; CHECK-NEXT: and %s0, -4, %s0 128; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 129; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 130; CHECK-NEXT: and %s0, %s1, (32)0 131; CHECK-NEXT: srl %s0, %s0, %s3 132; CHECK-NEXT: and %s0, %s0, (56)0 133; CHECK-NEXT: b.l.t (, %s10) 134 %3 = atomicrmw xchg ptr %0, i8 %1 monotonic 135 ret i8 %3 136} 137 138; Function Attrs: nofree norecurse nounwind mustprogress 139define signext i16 @_Z23atomic_swap_relaxed_i16RNSt3__16atomicIsEEs(ptr nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { 140; CHECK-LABEL: _Z23atomic_swap_relaxed_i16RNSt3__16atomicIsEEs: 141; CHECK: # %bb.0: 142; CHECK-NEXT: and %s2, 3, %s0 143; CHECK-NEXT: sla.w.sx %s3, %s2, 3 144; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 145; CHECK-NEXT: and %s0, -4, %s0 146; CHECK-NEXT: sla.w.sx %s2, (62)0, %s2 147; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 148; CHECK-NEXT: and %s0, %s1, (32)0 149; CHECK-NEXT: srl %s0, %s0, %s3 150; CHECK-NEXT: sll %s0, %s0, 48 151; CHECK-NEXT: sra.l %s0, %s0, 48 152; CHECK-NEXT: b.l.t (, %s10) 153 %3 = atomicrmw xchg ptr %0, i16 %1 monotonic 154 ret i16 %3 155} 156 157; Function Attrs: nofree norecurse nounwind mustprogress 158define zeroext i16 @_Z23atomic_swap_relaxed_u16RNSt3__16atomicItEEt(ptr nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { 159; CHECK-LABEL: _Z23atomic_swap_relaxed_u16RNSt3__16atomicItEEt: 160; CHECK: # %bb.0: 161; CHECK-NEXT: and %s2, 3, %s0 162; CHECK-NEXT: sla.w.sx %s3, %s2, 3 163; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 164; CHECK-NEXT: and %s0, -4, %s0 165; CHECK-NEXT: sla.w.sx %s2, (62)0, %s2 166; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 167; CHECK-NEXT: and %s0, %s1, (32)0 168; CHECK-NEXT: srl %s0, %s0, %s3 169; CHECK-NEXT: and %s0, %s0, (48)0 170; CHECK-NEXT: b.l.t (, %s10) 171 %3 = atomicrmw xchg ptr %0, i16 %1 monotonic 172 ret i16 %3 173} 174 175; Function Attrs: nofree norecurse nounwind mustprogress 176define signext i32 @_Z23atomic_swap_relaxed_i32RNSt3__16atomicIiEEi(ptr nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { 177; CHECK-LABEL: _Z23atomic_swap_relaxed_i32RNSt3__16atomicIiEEi: 178; CHECK: # %bb.0: 179; CHECK-NEXT: ts1am.w %s1, (%s0), 15 180; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 181; CHECK-NEXT: b.l.t (, %s10) 182 %3 = atomicrmw xchg ptr %0, i32 %1 monotonic 183 ret i32 %3 184} 185 186; Function Attrs: nofree norecurse nounwind mustprogress 187define zeroext i32 @_Z23atomic_swap_relaxed_u32RNSt3__16atomicIjEEj(ptr nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { 188; CHECK-LABEL: _Z23atomic_swap_relaxed_u32RNSt3__16atomicIjEEj: 189; CHECK: # %bb.0: 190; CHECK-NEXT: ts1am.w %s1, (%s0), 15 191; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 192; CHECK-NEXT: b.l.t (, %s10) 193 %3 = atomicrmw xchg ptr %0, i32 %1 monotonic 194 ret i32 %3 195} 196 197; Function Attrs: nofree norecurse nounwind mustprogress 198define i64 @_Z23atomic_swap_relaxed_i64RNSt3__16atomicIlEEl(ptr nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { 199; CHECK-LABEL: _Z23atomic_swap_relaxed_i64RNSt3__16atomicIlEEl: 200; CHECK: # %bb.0: 201; CHECK-NEXT: lea %s2, 255 202; CHECK-NEXT: ts1am.l %s1, (%s0), %s2 203; CHECK-NEXT: or %s0, 0, %s1 204; CHECK-NEXT: b.l.t (, %s10) 205 %3 = atomicrmw xchg ptr %0, i64 %1 monotonic 206 ret i64 %3 207} 208 209; Function Attrs: nofree norecurse nounwind mustprogress 210define i64 @_Z23atomic_swap_relaxed_u64RNSt3__16atomicImEEm(ptr nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { 211; CHECK-LABEL: _Z23atomic_swap_relaxed_u64RNSt3__16atomicImEEm: 212; CHECK: # %bb.0: 213; CHECK-NEXT: lea %s2, 255 214; CHECK-NEXT: ts1am.l %s1, (%s0), %s2 215; CHECK-NEXT: or %s0, 0, %s1 216; CHECK-NEXT: b.l.t (, %s10) 217 %3 = atomicrmw xchg ptr %0, i64 %1 monotonic 218 ret i64 %3 219} 220 221; Function Attrs: nounwind mustprogress 222define i128 @_Z24atomic_swap_relaxed_i128RNSt3__16atomicInEEn(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) { 223; CHECK-LABEL: _Z24atomic_swap_relaxed_i128RNSt3__16atomicInEEn: 224; CHECK: # %bb.0: 225; CHECK-NEXT: st %s9, (, %s11) 226; CHECK-NEXT: st %s10, 8(, %s11) 227; CHECK-NEXT: or %s9, 0, %s11 228; CHECK-NEXT: lea %s11, -272(, %s11) 229; CHECK-NEXT: brge.l.t %s11, %s8, .LBB9_2 230; CHECK-NEXT: # %bb.1: 231; CHECK-NEXT: ld %s61, 24(, %s14) 232; CHECK-NEXT: or %s62, 0, %s0 233; CHECK-NEXT: lea %s63, 315 234; CHECK-NEXT: shm.l %s63, (%s61) 235; CHECK-NEXT: shm.l %s8, 8(%s61) 236; CHECK-NEXT: shm.l %s11, 16(%s61) 237; CHECK-NEXT: monc 238; CHECK-NEXT: or %s0, 0, %s62 239; CHECK-NEXT: .LBB9_2: 240; CHECK-NEXT: or %s5, 0, %s0 241; CHECK-NEXT: st %s2, 264(, %s11) 242; CHECK-NEXT: st %s1, 256(, %s11) 243; CHECK-NEXT: lea %s0, __atomic_exchange@lo 244; CHECK-NEXT: and %s0, %s0, (32)0 245; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 246; CHECK-NEXT: lea %s2, 256(, %s11) 247; CHECK-NEXT: lea %s3, 240(, %s11) 248; CHECK-NEXT: or %s0, 16, (0)1 249; CHECK-NEXT: or %s4, 0, (0)1 250; CHECK-NEXT: or %s1, 0, %s5 251; CHECK-NEXT: bsic %s10, (, %s12) 252; CHECK-NEXT: ld %s1, 248(, %s11) 253; CHECK-NEXT: ld %s0, 240(, %s11) 254; CHECK-NEXT: or %s11, 0, %s9 255; CHECK-NEXT: ld %s10, 8(, %s11) 256; CHECK-NEXT: ld %s9, (, %s11) 257; CHECK-NEXT: b.l.t (, %s10) 258 %3 = alloca i128, align 16 259 %4 = alloca i128, align 16 260 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 261 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) 262 store i128 %1, ptr %3, align 16, !tbaa !2 263 call void @__atomic_exchange(i64 16, ptr nonnull %0, ptr nonnull %3, ptr nonnull %4, i32 signext 0) 264 %5 = load i128, ptr %4, align 16, !tbaa !2 265 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 266 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) 267 ret i128 %5 268} 269 270; Function Attrs: nounwind mustprogress 271define i128 @_Z24atomic_swap_relaxed_u128RNSt3__16atomicIoEEo(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) { 272; CHECK-LABEL: _Z24atomic_swap_relaxed_u128RNSt3__16atomicIoEEo: 273; CHECK: # %bb.0: 274; CHECK-NEXT: st %s9, (, %s11) 275; CHECK-NEXT: st %s10, 8(, %s11) 276; CHECK-NEXT: or %s9, 0, %s11 277; CHECK-NEXT: lea %s11, -272(, %s11) 278; CHECK-NEXT: brge.l.t %s11, %s8, .LBB10_2 279; CHECK-NEXT: # %bb.1: 280; CHECK-NEXT: ld %s61, 24(, %s14) 281; CHECK-NEXT: or %s62, 0, %s0 282; CHECK-NEXT: lea %s63, 315 283; CHECK-NEXT: shm.l %s63, (%s61) 284; CHECK-NEXT: shm.l %s8, 8(%s61) 285; CHECK-NEXT: shm.l %s11, 16(%s61) 286; CHECK-NEXT: monc 287; CHECK-NEXT: or %s0, 0, %s62 288; CHECK-NEXT: .LBB10_2: 289; CHECK-NEXT: or %s5, 0, %s0 290; CHECK-NEXT: st %s2, 264(, %s11) 291; CHECK-NEXT: st %s1, 256(, %s11) 292; CHECK-NEXT: lea %s0, __atomic_exchange@lo 293; CHECK-NEXT: and %s0, %s0, (32)0 294; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 295; CHECK-NEXT: lea %s2, 256(, %s11) 296; CHECK-NEXT: lea %s3, 240(, %s11) 297; CHECK-NEXT: or %s0, 16, (0)1 298; CHECK-NEXT: or %s4, 0, (0)1 299; CHECK-NEXT: or %s1, 0, %s5 300; CHECK-NEXT: bsic %s10, (, %s12) 301; CHECK-NEXT: ld %s1, 248(, %s11) 302; CHECK-NEXT: ld %s0, 240(, %s11) 303; CHECK-NEXT: or %s11, 0, %s9 304; CHECK-NEXT: ld %s10, 8(, %s11) 305; CHECK-NEXT: ld %s9, (, %s11) 306; CHECK-NEXT: b.l.t (, %s10) 307 %3 = alloca i128, align 16 308 %4 = alloca i128, align 16 309 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 310 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) 311 store i128 %1, ptr %3, align 16, !tbaa !2 312 call void @__atomic_exchange(i64 16, ptr nonnull %0, ptr nonnull %3, ptr nonnull %4, i32 signext 0) 313 %5 = load i128, ptr %4, align 16, !tbaa !2 314 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 315 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) 316 ret i128 %5 317} 318 319; Function Attrs: nofree norecurse nounwind mustprogress 320define zeroext i1 @_Z22atomic_swap_acquire_i1RNSt3__16atomicIbEEb(ptr nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { 321; CHECK-LABEL: _Z22atomic_swap_acquire_i1RNSt3__16atomicIbEEb: 322; CHECK: # %bb.0: 323; CHECK-NEXT: and %s2, 3, %s0 324; CHECK-NEXT: sla.w.sx %s3, %s2, 3 325; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 326; CHECK-NEXT: and %s0, -4, %s0 327; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 328; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 329; CHECK-NEXT: and %s0, %s1, (32)0 330; CHECK-NEXT: srl %s0, %s0, %s3 331; CHECK-NEXT: and %s0, 1, %s0 332; CHECK-NEXT: fencem 2 333; CHECK-NEXT: b.l.t (, %s10) 334 %3 = zext i1 %1 to i8 335 %4 = atomicrmw xchg ptr %0, i8 %3 acquire 336 %5 = and i8 %4, 1 337 %6 = icmp ne i8 %5, 0 338 ret i1 %6 339} 340 341; Function Attrs: nofree norecurse nounwind mustprogress 342define signext i8 @_Z22atomic_swap_acquire_i8RNSt3__16atomicIcEEc(ptr nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { 343; CHECK-LABEL: _Z22atomic_swap_acquire_i8RNSt3__16atomicIcEEc: 344; CHECK: # %bb.0: 345; CHECK-NEXT: and %s2, 3, %s0 346; CHECK-NEXT: sla.w.sx %s3, %s2, 3 347; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 348; CHECK-NEXT: and %s0, -4, %s0 349; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 350; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 351; CHECK-NEXT: and %s0, %s1, (32)0 352; CHECK-NEXT: srl %s0, %s0, %s3 353; CHECK-NEXT: sll %s0, %s0, 56 354; CHECK-NEXT: sra.l %s0, %s0, 56 355; CHECK-NEXT: fencem 2 356; CHECK-NEXT: b.l.t (, %s10) 357 %3 = atomicrmw xchg ptr %0, i8 %1 acquire 358 ret i8 %3 359} 360 361; Function Attrs: nofree norecurse nounwind mustprogress 362define zeroext i8 @_Z22atomic_swap_acquire_u8RNSt3__16atomicIhEEh(ptr nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { 363; CHECK-LABEL: _Z22atomic_swap_acquire_u8RNSt3__16atomicIhEEh: 364; CHECK: # %bb.0: 365; CHECK-NEXT: and %s2, 3, %s0 366; CHECK-NEXT: sla.w.sx %s3, %s2, 3 367; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 368; CHECK-NEXT: and %s0, -4, %s0 369; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 370; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 371; CHECK-NEXT: and %s0, %s1, (32)0 372; CHECK-NEXT: srl %s0, %s0, %s3 373; CHECK-NEXT: and %s0, %s0, (56)0 374; CHECK-NEXT: fencem 2 375; CHECK-NEXT: b.l.t (, %s10) 376 %3 = atomicrmw xchg ptr %0, i8 %1 acquire 377 ret i8 %3 378} 379 380; Function Attrs: nofree norecurse nounwind mustprogress 381define signext i16 @_Z23atomic_swap_acquire_i16RNSt3__16atomicIsEEs(ptr nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { 382; CHECK-LABEL: _Z23atomic_swap_acquire_i16RNSt3__16atomicIsEEs: 383; CHECK: # %bb.0: 384; CHECK-NEXT: and %s2, 3, %s0 385; CHECK-NEXT: sla.w.sx %s3, %s2, 3 386; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 387; CHECK-NEXT: and %s0, -4, %s0 388; CHECK-NEXT: sla.w.sx %s2, (62)0, %s2 389; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 390; CHECK-NEXT: and %s0, %s1, (32)0 391; CHECK-NEXT: srl %s0, %s0, %s3 392; CHECK-NEXT: sll %s0, %s0, 48 393; CHECK-NEXT: sra.l %s0, %s0, 48 394; CHECK-NEXT: fencem 2 395; CHECK-NEXT: b.l.t (, %s10) 396 %3 = atomicrmw xchg ptr %0, i16 %1 acquire 397 ret i16 %3 398} 399 400; Function Attrs: nofree norecurse nounwind mustprogress 401define zeroext i16 @_Z23atomic_swap_acquire_u16RNSt3__16atomicItEEt(ptr nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { 402; CHECK-LABEL: _Z23atomic_swap_acquire_u16RNSt3__16atomicItEEt: 403; CHECK: # %bb.0: 404; CHECK-NEXT: and %s2, 3, %s0 405; CHECK-NEXT: sla.w.sx %s3, %s2, 3 406; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 407; CHECK-NEXT: and %s0, -4, %s0 408; CHECK-NEXT: sla.w.sx %s2, (62)0, %s2 409; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 410; CHECK-NEXT: and %s0, %s1, (32)0 411; CHECK-NEXT: srl %s0, %s0, %s3 412; CHECK-NEXT: and %s0, %s0, (48)0 413; CHECK-NEXT: fencem 2 414; CHECK-NEXT: b.l.t (, %s10) 415 %3 = atomicrmw xchg ptr %0, i16 %1 acquire 416 ret i16 %3 417} 418 419; Function Attrs: nofree norecurse nounwind mustprogress 420define signext i32 @_Z23atomic_swap_acquire_i32RNSt3__16atomicIiEEi(ptr nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { 421; CHECK-LABEL: _Z23atomic_swap_acquire_i32RNSt3__16atomicIiEEi: 422; CHECK: # %bb.0: 423; CHECK-NEXT: ts1am.w %s1, (%s0), 15 424; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 425; CHECK-NEXT: fencem 2 426; CHECK-NEXT: b.l.t (, %s10) 427 %3 = atomicrmw xchg ptr %0, i32 %1 acquire 428 ret i32 %3 429} 430 431; Function Attrs: nofree norecurse nounwind mustprogress 432define zeroext i32 @_Z23atomic_swap_acquire_u32RNSt3__16atomicIjEEj(ptr nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { 433; CHECK-LABEL: _Z23atomic_swap_acquire_u32RNSt3__16atomicIjEEj: 434; CHECK: # %bb.0: 435; CHECK-NEXT: ts1am.w %s1, (%s0), 15 436; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 437; CHECK-NEXT: fencem 2 438; CHECK-NEXT: b.l.t (, %s10) 439 %3 = atomicrmw xchg ptr %0, i32 %1 acquire 440 ret i32 %3 441} 442 443; Function Attrs: nofree norecurse nounwind mustprogress 444define i64 @_Z23atomic_swap_acquire_i64RNSt3__16atomicIlEEl(ptr nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { 445; CHECK-LABEL: _Z23atomic_swap_acquire_i64RNSt3__16atomicIlEEl: 446; CHECK: # %bb.0: 447; CHECK-NEXT: lea %s2, 255 448; CHECK-NEXT: ts1am.l %s1, (%s0), %s2 449; CHECK-NEXT: fencem 2 450; CHECK-NEXT: or %s0, 0, %s1 451; CHECK-NEXT: b.l.t (, %s10) 452 %3 = atomicrmw xchg ptr %0, i64 %1 acquire 453 ret i64 %3 454} 455 456; Function Attrs: nofree norecurse nounwind mustprogress 457define i64 @_Z23atomic_swap_acquire_u64RNSt3__16atomicImEEm(ptr nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { 458; CHECK-LABEL: _Z23atomic_swap_acquire_u64RNSt3__16atomicImEEm: 459; CHECK: # %bb.0: 460; CHECK-NEXT: lea %s2, 255 461; CHECK-NEXT: ts1am.l %s1, (%s0), %s2 462; CHECK-NEXT: fencem 2 463; CHECK-NEXT: or %s0, 0, %s1 464; CHECK-NEXT: b.l.t (, %s10) 465 %3 = atomicrmw xchg ptr %0, i64 %1 acquire 466 ret i64 %3 467} 468 469; Function Attrs: nounwind mustprogress 470define i128 @_Z24atomic_swap_acquire_i128RNSt3__16atomicInEEn(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) { 471; CHECK-LABEL: _Z24atomic_swap_acquire_i128RNSt3__16atomicInEEn: 472; CHECK: # %bb.0: 473; CHECK-NEXT: st %s9, (, %s11) 474; CHECK-NEXT: st %s10, 8(, %s11) 475; CHECK-NEXT: or %s9, 0, %s11 476; CHECK-NEXT: lea %s11, -272(, %s11) 477; CHECK-NEXT: brge.l.t %s11, %s8, .LBB20_2 478; CHECK-NEXT: # %bb.1: 479; CHECK-NEXT: ld %s61, 24(, %s14) 480; CHECK-NEXT: or %s62, 0, %s0 481; CHECK-NEXT: lea %s63, 315 482; CHECK-NEXT: shm.l %s63, (%s61) 483; CHECK-NEXT: shm.l %s8, 8(%s61) 484; CHECK-NEXT: shm.l %s11, 16(%s61) 485; CHECK-NEXT: monc 486; CHECK-NEXT: or %s0, 0, %s62 487; CHECK-NEXT: .LBB20_2: 488; CHECK-NEXT: or %s5, 0, %s0 489; CHECK-NEXT: st %s2, 264(, %s11) 490; CHECK-NEXT: st %s1, 256(, %s11) 491; CHECK-NEXT: lea %s0, __atomic_exchange@lo 492; CHECK-NEXT: and %s0, %s0, (32)0 493; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 494; CHECK-NEXT: lea %s2, 256(, %s11) 495; CHECK-NEXT: lea %s3, 240(, %s11) 496; CHECK-NEXT: or %s0, 16, (0)1 497; CHECK-NEXT: or %s4, 2, (0)1 498; CHECK-NEXT: or %s1, 0, %s5 499; CHECK-NEXT: bsic %s10, (, %s12) 500; CHECK-NEXT: ld %s1, 248(, %s11) 501; CHECK-NEXT: ld %s0, 240(, %s11) 502; CHECK-NEXT: or %s11, 0, %s9 503; CHECK-NEXT: ld %s10, 8(, %s11) 504; CHECK-NEXT: ld %s9, (, %s11) 505; CHECK-NEXT: b.l.t (, %s10) 506 %3 = alloca i128, align 16 507 %4 = alloca i128, align 16 508 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 509 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) 510 store i128 %1, ptr %3, align 16, !tbaa !2 511 call void @__atomic_exchange(i64 16, ptr nonnull %0, ptr nonnull %3, ptr nonnull %4, i32 signext 2) 512 %5 = load i128, ptr %4, align 16, !tbaa !2 513 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 514 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) 515 ret i128 %5 516} 517 518; Function Attrs: nounwind mustprogress 519define i128 @_Z24atomic_swap_acquire_u128RNSt3__16atomicIoEEo(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) { 520; CHECK-LABEL: _Z24atomic_swap_acquire_u128RNSt3__16atomicIoEEo: 521; CHECK: # %bb.0: 522; CHECK-NEXT: st %s9, (, %s11) 523; CHECK-NEXT: st %s10, 8(, %s11) 524; CHECK-NEXT: or %s9, 0, %s11 525; CHECK-NEXT: lea %s11, -272(, %s11) 526; CHECK-NEXT: brge.l.t %s11, %s8, .LBB21_2 527; CHECK-NEXT: # %bb.1: 528; CHECK-NEXT: ld %s61, 24(, %s14) 529; CHECK-NEXT: or %s62, 0, %s0 530; CHECK-NEXT: lea %s63, 315 531; CHECK-NEXT: shm.l %s63, (%s61) 532; CHECK-NEXT: shm.l %s8, 8(%s61) 533; CHECK-NEXT: shm.l %s11, 16(%s61) 534; CHECK-NEXT: monc 535; CHECK-NEXT: or %s0, 0, %s62 536; CHECK-NEXT: .LBB21_2: 537; CHECK-NEXT: or %s5, 0, %s0 538; CHECK-NEXT: st %s2, 264(, %s11) 539; CHECK-NEXT: st %s1, 256(, %s11) 540; CHECK-NEXT: lea %s0, __atomic_exchange@lo 541; CHECK-NEXT: and %s0, %s0, (32)0 542; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 543; CHECK-NEXT: lea %s2, 256(, %s11) 544; CHECK-NEXT: lea %s3, 240(, %s11) 545; CHECK-NEXT: or %s0, 16, (0)1 546; CHECK-NEXT: or %s4, 2, (0)1 547; CHECK-NEXT: or %s1, 0, %s5 548; CHECK-NEXT: bsic %s10, (, %s12) 549; CHECK-NEXT: ld %s1, 248(, %s11) 550; CHECK-NEXT: ld %s0, 240(, %s11) 551; CHECK-NEXT: or %s11, 0, %s9 552; CHECK-NEXT: ld %s10, 8(, %s11) 553; CHECK-NEXT: ld %s9, (, %s11) 554; CHECK-NEXT: b.l.t (, %s10) 555 %3 = alloca i128, align 16 556 %4 = alloca i128, align 16 557 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 558 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) 559 store i128 %1, ptr %3, align 16, !tbaa !2 560 call void @__atomic_exchange(i64 16, ptr nonnull %0, ptr nonnull %3, ptr nonnull %4, i32 signext 2) 561 %5 = load i128, ptr %4, align 16, !tbaa !2 562 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 563 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) 564 ret i128 %5 565} 566 567; Function Attrs: nofree norecurse nounwind mustprogress 568define zeroext i1 @_Z22atomic_swap_seq_cst_i1RNSt3__16atomicIbEEb(ptr nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) { 569; CHECK-LABEL: _Z22atomic_swap_seq_cst_i1RNSt3__16atomicIbEEb: 570; CHECK: # %bb.0: 571; CHECK-NEXT: fencem 3 572; CHECK-NEXT: and %s2, 3, %s0 573; CHECK-NEXT: sla.w.sx %s3, %s2, 3 574; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 575; CHECK-NEXT: and %s0, -4, %s0 576; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 577; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 578; CHECK-NEXT: and %s0, %s1, (32)0 579; CHECK-NEXT: srl %s0, %s0, %s3 580; CHECK-NEXT: and %s0, 1, %s0 581; CHECK-NEXT: fencem 3 582; CHECK-NEXT: b.l.t (, %s10) 583 %3 = zext i1 %1 to i8 584 %4 = atomicrmw xchg ptr %0, i8 %3 seq_cst 585 %5 = and i8 %4, 1 586 %6 = icmp ne i8 %5, 0 587 ret i1 %6 588} 589 590; Function Attrs: nofree norecurse nounwind mustprogress 591define signext i8 @_Z22atomic_swap_seq_cst_i8RNSt3__16atomicIcEEc(ptr nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) { 592; CHECK-LABEL: _Z22atomic_swap_seq_cst_i8RNSt3__16atomicIcEEc: 593; CHECK: # %bb.0: 594; CHECK-NEXT: fencem 3 595; CHECK-NEXT: and %s2, 3, %s0 596; CHECK-NEXT: sla.w.sx %s3, %s2, 3 597; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 598; CHECK-NEXT: and %s0, -4, %s0 599; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 600; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 601; CHECK-NEXT: and %s0, %s1, (32)0 602; CHECK-NEXT: srl %s0, %s0, %s3 603; CHECK-NEXT: sll %s0, %s0, 56 604; CHECK-NEXT: sra.l %s0, %s0, 56 605; CHECK-NEXT: fencem 3 606; CHECK-NEXT: b.l.t (, %s10) 607 %3 = atomicrmw xchg ptr %0, i8 %1 seq_cst 608 ret i8 %3 609} 610 611; Function Attrs: nofree norecurse nounwind mustprogress 612define zeroext i8 @_Z22atomic_swap_seq_cst_u8RNSt3__16atomicIhEEh(ptr nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) { 613; CHECK-LABEL: _Z22atomic_swap_seq_cst_u8RNSt3__16atomicIhEEh: 614; CHECK: # %bb.0: 615; CHECK-NEXT: fencem 3 616; CHECK-NEXT: and %s2, 3, %s0 617; CHECK-NEXT: sla.w.sx %s3, %s2, 3 618; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 619; CHECK-NEXT: and %s0, -4, %s0 620; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 621; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 622; CHECK-NEXT: and %s0, %s1, (32)0 623; CHECK-NEXT: srl %s0, %s0, %s3 624; CHECK-NEXT: and %s0, %s0, (56)0 625; CHECK-NEXT: fencem 3 626; CHECK-NEXT: b.l.t (, %s10) 627 %3 = atomicrmw xchg ptr %0, i8 %1 seq_cst 628 ret i8 %3 629} 630 631; Function Attrs: nofree norecurse nounwind mustprogress 632define signext i16 @_Z23atomic_swap_seq_cst_i16RNSt3__16atomicIsEEs(ptr nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) { 633; CHECK-LABEL: _Z23atomic_swap_seq_cst_i16RNSt3__16atomicIsEEs: 634; CHECK: # %bb.0: 635; CHECK-NEXT: fencem 3 636; CHECK-NEXT: and %s2, 3, %s0 637; CHECK-NEXT: sla.w.sx %s3, %s2, 3 638; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 639; CHECK-NEXT: and %s0, -4, %s0 640; CHECK-NEXT: sla.w.sx %s2, (62)0, %s2 641; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 642; CHECK-NEXT: and %s0, %s1, (32)0 643; CHECK-NEXT: srl %s0, %s0, %s3 644; CHECK-NEXT: sll %s0, %s0, 48 645; CHECK-NEXT: sra.l %s0, %s0, 48 646; CHECK-NEXT: fencem 3 647; CHECK-NEXT: b.l.t (, %s10) 648 %3 = atomicrmw xchg ptr %0, i16 %1 seq_cst 649 ret i16 %3 650} 651 652; Function Attrs: nofree norecurse nounwind mustprogress 653define zeroext i16 @_Z23atomic_swap_seq_cst_u16RNSt3__16atomicItEEt(ptr nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) { 654; CHECK-LABEL: _Z23atomic_swap_seq_cst_u16RNSt3__16atomicItEEt: 655; CHECK: # %bb.0: 656; CHECK-NEXT: fencem 3 657; CHECK-NEXT: and %s2, 3, %s0 658; CHECK-NEXT: sla.w.sx %s3, %s2, 3 659; CHECK-NEXT: sla.w.sx %s1, %s1, %s3 660; CHECK-NEXT: and %s0, -4, %s0 661; CHECK-NEXT: sla.w.sx %s2, (62)0, %s2 662; CHECK-NEXT: ts1am.w %s1, (%s0), %s2 663; CHECK-NEXT: and %s0, %s1, (32)0 664; CHECK-NEXT: srl %s0, %s0, %s3 665; CHECK-NEXT: and %s0, %s0, (48)0 666; CHECK-NEXT: fencem 3 667; CHECK-NEXT: b.l.t (, %s10) 668 %3 = atomicrmw xchg ptr %0, i16 %1 seq_cst 669 ret i16 %3 670} 671 672; Function Attrs: nofree norecurse nounwind mustprogress 673define signext i32 @_Z23atomic_swap_seq_cst_i32RNSt3__16atomicIiEEi(ptr nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) { 674; CHECK-LABEL: _Z23atomic_swap_seq_cst_i32RNSt3__16atomicIiEEi: 675; CHECK: # %bb.0: 676; CHECK-NEXT: fencem 3 677; CHECK-NEXT: ts1am.w %s1, (%s0), 15 678; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 679; CHECK-NEXT: fencem 3 680; CHECK-NEXT: b.l.t (, %s10) 681 %3 = atomicrmw xchg ptr %0, i32 %1 seq_cst 682 ret i32 %3 683} 684 685; Function Attrs: nofree norecurse nounwind mustprogress 686define zeroext i32 @_Z23atomic_swap_seq_cst_u32RNSt3__16atomicIjEEj(ptr nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) { 687; CHECK-LABEL: _Z23atomic_swap_seq_cst_u32RNSt3__16atomicIjEEj: 688; CHECK: # %bb.0: 689; CHECK-NEXT: fencem 3 690; CHECK-NEXT: ts1am.w %s1, (%s0), 15 691; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1 692; CHECK-NEXT: fencem 3 693; CHECK-NEXT: b.l.t (, %s10) 694 %3 = atomicrmw xchg ptr %0, i32 %1 seq_cst 695 ret i32 %3 696} 697 698; Function Attrs: nofree norecurse nounwind mustprogress 699define i64 @_Z23atomic_swap_seq_cst_i64RNSt3__16atomicIlEEl(ptr nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { 700; CHECK-LABEL: _Z23atomic_swap_seq_cst_i64RNSt3__16atomicIlEEl: 701; CHECK: # %bb.0: 702; CHECK-NEXT: fencem 3 703; CHECK-NEXT: lea %s2, 255 704; CHECK-NEXT: ts1am.l %s1, (%s0), %s2 705; CHECK-NEXT: fencem 3 706; CHECK-NEXT: or %s0, 0, %s1 707; CHECK-NEXT: b.l.t (, %s10) 708 %3 = atomicrmw xchg ptr %0, i64 %1 seq_cst 709 ret i64 %3 710} 711 712; Function Attrs: nofree norecurse nounwind mustprogress 713define i64 @_Z23atomic_swap_seq_cst_u64RNSt3__16atomicImEEm(ptr nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) { 714; CHECK-LABEL: _Z23atomic_swap_seq_cst_u64RNSt3__16atomicImEEm: 715; CHECK: # %bb.0: 716; CHECK-NEXT: fencem 3 717; CHECK-NEXT: lea %s2, 255 718; CHECK-NEXT: ts1am.l %s1, (%s0), %s2 719; CHECK-NEXT: fencem 3 720; CHECK-NEXT: or %s0, 0, %s1 721; CHECK-NEXT: b.l.t (, %s10) 722 %3 = atomicrmw xchg ptr %0, i64 %1 seq_cst 723 ret i64 %3 724} 725 726; Function Attrs: nounwind mustprogress 727define i128 @_Z24atomic_swap_seq_cst_i128RNSt3__16atomicInEEn(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) { 728; CHECK-LABEL: _Z24atomic_swap_seq_cst_i128RNSt3__16atomicInEEn: 729; CHECK: # %bb.0: 730; CHECK-NEXT: st %s9, (, %s11) 731; CHECK-NEXT: st %s10, 8(, %s11) 732; CHECK-NEXT: or %s9, 0, %s11 733; CHECK-NEXT: lea %s11, -272(, %s11) 734; CHECK-NEXT: brge.l.t %s11, %s8, .LBB31_2 735; CHECK-NEXT: # %bb.1: 736; CHECK-NEXT: ld %s61, 24(, %s14) 737; CHECK-NEXT: or %s62, 0, %s0 738; CHECK-NEXT: lea %s63, 315 739; CHECK-NEXT: shm.l %s63, (%s61) 740; CHECK-NEXT: shm.l %s8, 8(%s61) 741; CHECK-NEXT: shm.l %s11, 16(%s61) 742; CHECK-NEXT: monc 743; CHECK-NEXT: or %s0, 0, %s62 744; CHECK-NEXT: .LBB31_2: 745; CHECK-NEXT: or %s5, 0, %s0 746; CHECK-NEXT: st %s2, 264(, %s11) 747; CHECK-NEXT: st %s1, 256(, %s11) 748; CHECK-NEXT: lea %s0, __atomic_exchange@lo 749; CHECK-NEXT: and %s0, %s0, (32)0 750; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 751; CHECK-NEXT: lea %s2, 256(, %s11) 752; CHECK-NEXT: lea %s3, 240(, %s11) 753; CHECK-NEXT: or %s0, 16, (0)1 754; CHECK-NEXT: or %s4, 5, (0)1 755; CHECK-NEXT: or %s1, 0, %s5 756; CHECK-NEXT: bsic %s10, (, %s12) 757; CHECK-NEXT: ld %s1, 248(, %s11) 758; CHECK-NEXT: ld %s0, 240(, %s11) 759; CHECK-NEXT: or %s11, 0, %s9 760; CHECK-NEXT: ld %s10, 8(, %s11) 761; CHECK-NEXT: ld %s9, (, %s11) 762; CHECK-NEXT: b.l.t (, %s10) 763 %3 = alloca i128, align 16 764 %4 = alloca i128, align 16 765 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 766 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) 767 store i128 %1, ptr %3, align 16, !tbaa !2 768 call void @__atomic_exchange(i64 16, ptr nonnull %0, ptr nonnull %3, ptr nonnull %4, i32 signext 5) 769 %5 = load i128, ptr %4, align 16, !tbaa !2 770 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 771 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) 772 ret i128 %5 773} 774 775; Function Attrs: nounwind mustprogress 776define i128 @_Z24atomic_swap_seq_cst_u128RNSt3__16atomicIoEEo(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) { 777; CHECK-LABEL: _Z24atomic_swap_seq_cst_u128RNSt3__16atomicIoEEo: 778; CHECK: # %bb.0: 779; CHECK-NEXT: st %s9, (, %s11) 780; CHECK-NEXT: st %s10, 8(, %s11) 781; CHECK-NEXT: or %s9, 0, %s11 782; CHECK-NEXT: lea %s11, -272(, %s11) 783; CHECK-NEXT: brge.l.t %s11, %s8, .LBB32_2 784; CHECK-NEXT: # %bb.1: 785; CHECK-NEXT: ld %s61, 24(, %s14) 786; CHECK-NEXT: or %s62, 0, %s0 787; CHECK-NEXT: lea %s63, 315 788; CHECK-NEXT: shm.l %s63, (%s61) 789; CHECK-NEXT: shm.l %s8, 8(%s61) 790; CHECK-NEXT: shm.l %s11, 16(%s61) 791; CHECK-NEXT: monc 792; CHECK-NEXT: or %s0, 0, %s62 793; CHECK-NEXT: .LBB32_2: 794; CHECK-NEXT: or %s5, 0, %s0 795; CHECK-NEXT: st %s2, 264(, %s11) 796; CHECK-NEXT: st %s1, 256(, %s11) 797; CHECK-NEXT: lea %s0, __atomic_exchange@lo 798; CHECK-NEXT: and %s0, %s0, (32)0 799; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 800; CHECK-NEXT: lea %s2, 256(, %s11) 801; CHECK-NEXT: lea %s3, 240(, %s11) 802; CHECK-NEXT: or %s0, 16, (0)1 803; CHECK-NEXT: or %s4, 5, (0)1 804; CHECK-NEXT: or %s1, 0, %s5 805; CHECK-NEXT: bsic %s10, (, %s12) 806; CHECK-NEXT: ld %s1, 248(, %s11) 807; CHECK-NEXT: ld %s0, 240(, %s11) 808; CHECK-NEXT: or %s11, 0, %s9 809; CHECK-NEXT: ld %s10, 8(, %s11) 810; CHECK-NEXT: ld %s9, (, %s11) 811; CHECK-NEXT: b.l.t (, %s10) 812 %3 = alloca i128, align 16 813 %4 = alloca i128, align 16 814 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 815 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) 816 store i128 %1, ptr %3, align 16, !tbaa !2 817 call void @__atomic_exchange(i64 16, ptr nonnull %0, ptr nonnull %3, ptr nonnull %4, i32 signext 5) 818 %5 = load i128, ptr %4, align 16, !tbaa !2 819 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 820 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) 821 ret i128 %5 822} 823 824; Function Attrs: nofree nounwind mustprogress 825define zeroext i1 @_Z26atomic_swap_relaxed_stk_i1b(i1 zeroext %0) { 826; CHECK-LABEL: _Z26atomic_swap_relaxed_stk_i1b: 827; CHECK: # %bb.0: 828; CHECK-NEXT: adds.l %s11, -16, %s11 829; CHECK-NEXT: brge.l.t %s11, %s8, .LBB33_2 830; CHECK-NEXT: # %bb.1: 831; CHECK-NEXT: ld %s61, 24(, %s14) 832; CHECK-NEXT: or %s62, 0, %s0 833; CHECK-NEXT: lea %s63, 315 834; CHECK-NEXT: shm.l %s63, (%s61) 835; CHECK-NEXT: shm.l %s8, 8(%s61) 836; CHECK-NEXT: shm.l %s11, 16(%s61) 837; CHECK-NEXT: monc 838; CHECK-NEXT: or %s0, 0, %s62 839; CHECK-NEXT: .LBB33_2: 840; CHECK-NEXT: and %s0, %s0, (32)0 841; CHECK-NEXT: or %s1, 1, (0)1 842; CHECK-NEXT: lea %s2, 8(, %s11) 843; CHECK-NEXT: ts1am.w %s0, (%s2), %s1 844; CHECK-NEXT: and %s0, 1, %s0 845; CHECK-NEXT: adds.l %s11, 16, %s11 846; CHECK-NEXT: b.l.t (, %s10) 847 %2 = alloca %"struct.std::__1::atomic", align 8 848 call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) 849 %3 = zext i1 %0 to i8 850 %4 = atomicrmw volatile xchg ptr %2, i8 %3 monotonic 851 %5 = and i8 %4, 1 852 %6 = icmp ne i8 %5, 0 853 call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) 854 ret i1 %6 855} 856 857; Function Attrs: argmemonly nofree nosync nounwind willreturn 858declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) 859 860; Function Attrs: argmemonly nofree nosync nounwind willreturn 861declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) 862 863; Function Attrs: nofree nounwind mustprogress 864define signext i8 @_Z26atomic_swap_relaxed_stk_i8c(i8 signext %0) { 865; CHECK-LABEL: _Z26atomic_swap_relaxed_stk_i8c: 866; CHECK: # %bb.0: 867; CHECK-NEXT: adds.l %s11, -16, %s11 868; CHECK-NEXT: brge.l.t %s11, %s8, .LBB34_2 869; CHECK-NEXT: # %bb.1: 870; CHECK-NEXT: ld %s61, 24(, %s14) 871; CHECK-NEXT: or %s62, 0, %s0 872; CHECK-NEXT: lea %s63, 315 873; CHECK-NEXT: shm.l %s63, (%s61) 874; CHECK-NEXT: shm.l %s8, 8(%s61) 875; CHECK-NEXT: shm.l %s11, 16(%s61) 876; CHECK-NEXT: monc 877; CHECK-NEXT: or %s0, 0, %s62 878; CHECK-NEXT: .LBB34_2: 879; CHECK-NEXT: and %s0, %s0, (32)0 880; CHECK-NEXT: or %s1, 1, (0)1 881; CHECK-NEXT: lea %s2, 8(, %s11) 882; CHECK-NEXT: ts1am.w %s0, (%s2), %s1 883; CHECK-NEXT: sll %s0, %s0, 56 884; CHECK-NEXT: sra.l %s0, %s0, 56 885; CHECK-NEXT: adds.l %s11, 16, %s11 886; CHECK-NEXT: b.l.t (, %s10) 887 %2 = alloca %"struct.std::__1::atomic.0", align 8 888 call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) 889 %3 = atomicrmw volatile xchg ptr %2, i8 %0 monotonic 890 call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) 891 ret i8 %3 892} 893 894; Function Attrs: nofree nounwind mustprogress 895define zeroext i8 @_Z26atomic_swap_relaxed_stk_u8h(i8 zeroext %0) { 896; CHECK-LABEL: _Z26atomic_swap_relaxed_stk_u8h: 897; CHECK: # %bb.0: 898; CHECK-NEXT: adds.l %s11, -16, %s11 899; CHECK-NEXT: brge.l.t %s11, %s8, .LBB35_2 900; CHECK-NEXT: # %bb.1: 901; CHECK-NEXT: ld %s61, 24(, %s14) 902; CHECK-NEXT: or %s62, 0, %s0 903; CHECK-NEXT: lea %s63, 315 904; CHECK-NEXT: shm.l %s63, (%s61) 905; CHECK-NEXT: shm.l %s8, 8(%s61) 906; CHECK-NEXT: shm.l %s11, 16(%s61) 907; CHECK-NEXT: monc 908; CHECK-NEXT: or %s0, 0, %s62 909; CHECK-NEXT: .LBB35_2: 910; CHECK-NEXT: and %s0, %s0, (32)0 911; CHECK-NEXT: or %s1, 1, (0)1 912; CHECK-NEXT: lea %s2, 8(, %s11) 913; CHECK-NEXT: ts1am.w %s0, (%s2), %s1 914; CHECK-NEXT: and %s0, %s0, (56)0 915; CHECK-NEXT: adds.l %s11, 16, %s11 916; CHECK-NEXT: b.l.t (, %s10) 917 %2 = alloca %"struct.std::__1::atomic.5", align 8 918 call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) 919 %3 = atomicrmw volatile xchg ptr %2, i8 %0 monotonic 920 call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) 921 ret i8 %3 922} 923 924; Function Attrs: nofree nounwind mustprogress 925define signext i16 @_Z27atomic_swap_relaxed_stk_i16s(i16 signext %0) { 926; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_i16s: 927; CHECK: # %bb.0: 928; CHECK-NEXT: adds.l %s11, -16, %s11 929; CHECK-NEXT: brge.l.t %s11, %s8, .LBB36_2 930; CHECK-NEXT: # %bb.1: 931; CHECK-NEXT: ld %s61, 24(, %s14) 932; CHECK-NEXT: or %s62, 0, %s0 933; CHECK-NEXT: lea %s63, 315 934; CHECK-NEXT: shm.l %s63, (%s61) 935; CHECK-NEXT: shm.l %s8, 8(%s61) 936; CHECK-NEXT: shm.l %s11, 16(%s61) 937; CHECK-NEXT: monc 938; CHECK-NEXT: or %s0, 0, %s62 939; CHECK-NEXT: .LBB36_2: 940; CHECK-NEXT: and %s0, %s0, (32)0 941; CHECK-NEXT: or %s1, 3, (0)1 942; CHECK-NEXT: lea %s2, 8(, %s11) 943; CHECK-NEXT: ts1am.w %s0, (%s2), %s1 944; CHECK-NEXT: sll %s0, %s0, 48 945; CHECK-NEXT: sra.l %s0, %s0, 48 946; CHECK-NEXT: adds.l %s11, 16, %s11 947; CHECK-NEXT: b.l.t (, %s10) 948 %2 = alloca %"struct.std::__1::atomic.10", align 8 949 call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %2) 950 %3 = atomicrmw volatile xchg ptr %2, i16 %0 monotonic 951 call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %2) 952 ret i16 %3 953} 954 955; Function Attrs: nofree nounwind mustprogress 956define zeroext i16 @_Z27atomic_swap_relaxed_stk_u16t(i16 zeroext %0) { 957; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_u16t: 958; CHECK: # %bb.0: 959; CHECK-NEXT: adds.l %s11, -16, %s11 960; CHECK-NEXT: brge.l.t %s11, %s8, .LBB37_2 961; CHECK-NEXT: # %bb.1: 962; CHECK-NEXT: ld %s61, 24(, %s14) 963; CHECK-NEXT: or %s62, 0, %s0 964; CHECK-NEXT: lea %s63, 315 965; CHECK-NEXT: shm.l %s63, (%s61) 966; CHECK-NEXT: shm.l %s8, 8(%s61) 967; CHECK-NEXT: shm.l %s11, 16(%s61) 968; CHECK-NEXT: monc 969; CHECK-NEXT: or %s0, 0, %s62 970; CHECK-NEXT: .LBB37_2: 971; CHECK-NEXT: and %s0, %s0, (32)0 972; CHECK-NEXT: or %s1, 3, (0)1 973; CHECK-NEXT: lea %s2, 8(, %s11) 974; CHECK-NEXT: ts1am.w %s0, (%s2), %s1 975; CHECK-NEXT: and %s0, %s0, (48)0 976; CHECK-NEXT: adds.l %s11, 16, %s11 977; CHECK-NEXT: b.l.t (, %s10) 978 %2 = alloca %"struct.std::__1::atomic.15", align 8 979 call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %2) 980 %3 = atomicrmw volatile xchg ptr %2, i16 %0 monotonic 981 call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %2) 982 ret i16 %3 983} 984 985; Function Attrs: nofree nounwind mustprogress 986define signext i32 @_Z27atomic_swap_relaxed_stk_i32i(i32 signext %0) { 987; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_i32i: 988; CHECK: # %bb.0: 989; CHECK-NEXT: adds.l %s11, -16, %s11 990; CHECK-NEXT: brge.l.t %s11, %s8, .LBB38_2 991; CHECK-NEXT: # %bb.1: 992; CHECK-NEXT: ld %s61, 24(, %s14) 993; CHECK-NEXT: or %s62, 0, %s0 994; CHECK-NEXT: lea %s63, 315 995; CHECK-NEXT: shm.l %s63, (%s61) 996; CHECK-NEXT: shm.l %s8, 8(%s61) 997; CHECK-NEXT: shm.l %s11, 16(%s61) 998; CHECK-NEXT: monc 999; CHECK-NEXT: or %s0, 0, %s62 1000; CHECK-NEXT: .LBB38_2: 1001; CHECK-NEXT: ts1am.w %s0, 8(%s11), 15 1002; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 1003; CHECK-NEXT: adds.l %s11, 16, %s11 1004; CHECK-NEXT: b.l.t (, %s10) 1005 %2 = alloca %"struct.std::__1::atomic.20", align 8 1006 call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) 1007 %3 = atomicrmw volatile xchg ptr %2, i32 %0 monotonic 1008 call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) 1009 ret i32 %3 1010} 1011 1012; Function Attrs: nofree nounwind mustprogress 1013define zeroext i32 @_Z27atomic_swap_relaxed_stk_u32j(i32 zeroext %0) { 1014; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_u32j: 1015; CHECK: # %bb.0: 1016; CHECK-NEXT: adds.l %s11, -16, %s11 1017; CHECK-NEXT: brge.l.t %s11, %s8, .LBB39_2 1018; CHECK-NEXT: # %bb.1: 1019; CHECK-NEXT: ld %s61, 24(, %s14) 1020; CHECK-NEXT: or %s62, 0, %s0 1021; CHECK-NEXT: lea %s63, 315 1022; CHECK-NEXT: shm.l %s63, (%s61) 1023; CHECK-NEXT: shm.l %s8, 8(%s61) 1024; CHECK-NEXT: shm.l %s11, 16(%s61) 1025; CHECK-NEXT: monc 1026; CHECK-NEXT: or %s0, 0, %s62 1027; CHECK-NEXT: .LBB39_2: 1028; CHECK-NEXT: ts1am.w %s0, 8(%s11), 15 1029; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 1030; CHECK-NEXT: adds.l %s11, 16, %s11 1031; CHECK-NEXT: b.l.t (, %s10) 1032 %2 = alloca %"struct.std::__1::atomic.25", align 8 1033 call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) 1034 %3 = atomicrmw volatile xchg ptr %2, i32 %0 monotonic 1035 call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) 1036 ret i32 %3 1037} 1038 1039; Function Attrs: nofree nounwind mustprogress 1040define i64 @_Z27atomic_swap_relaxed_stk_i64l(i64 %0) { 1041; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_i64l: 1042; CHECK: # %bb.0: 1043; CHECK-NEXT: adds.l %s11, -16, %s11 1044; CHECK-NEXT: brge.l.t %s11, %s8, .LBB40_2 1045; CHECK-NEXT: # %bb.1: 1046; CHECK-NEXT: ld %s61, 24(, %s14) 1047; CHECK-NEXT: or %s62, 0, %s0 1048; CHECK-NEXT: lea %s63, 315 1049; CHECK-NEXT: shm.l %s63, (%s61) 1050; CHECK-NEXT: shm.l %s8, 8(%s61) 1051; CHECK-NEXT: shm.l %s11, 16(%s61) 1052; CHECK-NEXT: monc 1053; CHECK-NEXT: or %s0, 0, %s62 1054; CHECK-NEXT: .LBB40_2: 1055; CHECK-NEXT: lea %s1, 255 1056; CHECK-NEXT: ts1am.l %s0, 8(%s11), %s1 1057; CHECK-NEXT: adds.l %s11, 16, %s11 1058; CHECK-NEXT: b.l.t (, %s10) 1059 %2 = alloca %"struct.std::__1::atomic.30", align 8 1060 call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) 1061 %3 = atomicrmw volatile xchg ptr %2, i64 %0 monotonic 1062 call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) 1063 ret i64 %3 1064} 1065 1066; Function Attrs: nofree nounwind mustprogress 1067define i64 @_Z27atomic_swap_relaxed_stk_u64m(i64 %0) { 1068; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_u64m: 1069; CHECK: # %bb.0: 1070; CHECK-NEXT: adds.l %s11, -16, %s11 1071; CHECK-NEXT: brge.l.t %s11, %s8, .LBB41_2 1072; CHECK-NEXT: # %bb.1: 1073; CHECK-NEXT: ld %s61, 24(, %s14) 1074; CHECK-NEXT: or %s62, 0, %s0 1075; CHECK-NEXT: lea %s63, 315 1076; CHECK-NEXT: shm.l %s63, (%s61) 1077; CHECK-NEXT: shm.l %s8, 8(%s61) 1078; CHECK-NEXT: shm.l %s11, 16(%s61) 1079; CHECK-NEXT: monc 1080; CHECK-NEXT: or %s0, 0, %s62 1081; CHECK-NEXT: .LBB41_2: 1082; CHECK-NEXT: lea %s1, 255 1083; CHECK-NEXT: ts1am.l %s0, 8(%s11), %s1 1084; CHECK-NEXT: adds.l %s11, 16, %s11 1085; CHECK-NEXT: b.l.t (, %s10) 1086 %2 = alloca %"struct.std::__1::atomic.35", align 8 1087 call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) 1088 %3 = atomicrmw volatile xchg ptr %2, i64 %0 monotonic 1089 call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) 1090 ret i64 %3 1091} 1092 1093; Function Attrs: nounwind mustprogress 1094define i128 @_Z28atomic_swap_relaxed_stk_i128n(i128 %0) { 1095; CHECK-LABEL: _Z28atomic_swap_relaxed_stk_i128n: 1096; CHECK: # %bb.0: 1097; CHECK-NEXT: st %s9, (, %s11) 1098; CHECK-NEXT: st %s10, 8(, %s11) 1099; CHECK-NEXT: or %s9, 0, %s11 1100; CHECK-NEXT: lea %s11, -288(, %s11) 1101; CHECK-NEXT: brge.l.t %s11, %s8, .LBB42_2 1102; CHECK-NEXT: # %bb.1: 1103; CHECK-NEXT: ld %s61, 24(, %s14) 1104; CHECK-NEXT: or %s62, 0, %s0 1105; CHECK-NEXT: lea %s63, 315 1106; CHECK-NEXT: shm.l %s63, (%s61) 1107; CHECK-NEXT: shm.l %s8, 8(%s61) 1108; CHECK-NEXT: shm.l %s11, 16(%s61) 1109; CHECK-NEXT: monc 1110; CHECK-NEXT: or %s0, 0, %s62 1111; CHECK-NEXT: .LBB42_2: 1112; CHECK-NEXT: st %s1, 280(, %s11) 1113; CHECK-NEXT: st %s0, 272(, %s11) 1114; CHECK-NEXT: lea %s0, __atomic_exchange@lo 1115; CHECK-NEXT: and %s0, %s0, (32)0 1116; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 1117; CHECK-NEXT: lea %s1, 240(, %s11) 1118; CHECK-NEXT: lea %s2, 272(, %s11) 1119; CHECK-NEXT: lea %s3, 256(, %s11) 1120; CHECK-NEXT: or %s0, 16, (0)1 1121; CHECK-NEXT: or %s4, 0, (0)1 1122; CHECK-NEXT: bsic %s10, (, %s12) 1123; CHECK-NEXT: ld %s1, 264(, %s11) 1124; CHECK-NEXT: ld %s0, 256(, %s11) 1125; CHECK-NEXT: or %s11, 0, %s9 1126; CHECK-NEXT: ld %s10, 8(, %s11) 1127; CHECK-NEXT: ld %s9, (, %s11) 1128; CHECK-NEXT: b.l.t (, %s10) 1129 %2 = alloca i128, align 16 1130 %3 = alloca i128, align 16 1131 %4 = alloca %"struct.std::__1::atomic.40", align 16 1132 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) 1133 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2) 1134 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 1135 store i128 %0, ptr %2, align 16, !tbaa !2 1136 call void @__atomic_exchange(i64 16, ptr nonnull %4, ptr nonnull %2, ptr nonnull %3, i32 signext 0) 1137 %5 = load i128, ptr %3, align 16, !tbaa !2 1138 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %2) 1139 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 1140 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) 1141 ret i128 %5 1142} 1143 1144; Function Attrs: nounwind mustprogress 1145define i128 @_Z28atomic_swap_relaxed_stk_u128o(i128 %0) { 1146; CHECK-LABEL: _Z28atomic_swap_relaxed_stk_u128o: 1147; CHECK: # %bb.0: 1148; CHECK-NEXT: st %s9, (, %s11) 1149; CHECK-NEXT: st %s10, 8(, %s11) 1150; CHECK-NEXT: or %s9, 0, %s11 1151; CHECK-NEXT: lea %s11, -288(, %s11) 1152; CHECK-NEXT: brge.l.t %s11, %s8, .LBB43_2 1153; CHECK-NEXT: # %bb.1: 1154; CHECK-NEXT: ld %s61, 24(, %s14) 1155; CHECK-NEXT: or %s62, 0, %s0 1156; CHECK-NEXT: lea %s63, 315 1157; CHECK-NEXT: shm.l %s63, (%s61) 1158; CHECK-NEXT: shm.l %s8, 8(%s61) 1159; CHECK-NEXT: shm.l %s11, 16(%s61) 1160; CHECK-NEXT: monc 1161; CHECK-NEXT: or %s0, 0, %s62 1162; CHECK-NEXT: .LBB43_2: 1163; CHECK-NEXT: st %s1, 280(, %s11) 1164; CHECK-NEXT: st %s0, 272(, %s11) 1165; CHECK-NEXT: lea %s0, __atomic_exchange@lo 1166; CHECK-NEXT: and %s0, %s0, (32)0 1167; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 1168; CHECK-NEXT: lea %s1, 240(, %s11) 1169; CHECK-NEXT: lea %s2, 272(, %s11) 1170; CHECK-NEXT: lea %s3, 256(, %s11) 1171; CHECK-NEXT: or %s0, 16, (0)1 1172; CHECK-NEXT: or %s4, 0, (0)1 1173; CHECK-NEXT: bsic %s10, (, %s12) 1174; CHECK-NEXT: ld %s1, 264(, %s11) 1175; CHECK-NEXT: ld %s0, 256(, %s11) 1176; CHECK-NEXT: or %s11, 0, %s9 1177; CHECK-NEXT: ld %s10, 8(, %s11) 1178; CHECK-NEXT: ld %s9, (, %s11) 1179; CHECK-NEXT: b.l.t (, %s10) 1180 %2 = alloca i128, align 16 1181 %3 = alloca i128, align 16 1182 %4 = alloca %"struct.std::__1::atomic.45", align 16 1183 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) 1184 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2) 1185 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 1186 store i128 %0, ptr %2, align 16, !tbaa !2 1187 call void @__atomic_exchange(i64 16, ptr nonnull %4, ptr nonnull %2, ptr nonnull %3, i32 signext 0) 1188 %5 = load i128, ptr %3, align 16, !tbaa !2 1189 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %2) 1190 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 1191 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) 1192 ret i128 %5 1193} 1194 1195; Function Attrs: nofree norecurse nounwind mustprogress 1196define zeroext i1 @_Z25atomic_swap_relaxed_gv_i1b(i1 zeroext %0) { 1197; CHECK-LABEL: _Z25atomic_swap_relaxed_gv_i1b: 1198; CHECK: # %bb.0: 1199; CHECK-NEXT: lea %s1, gv_i1@lo 1200; CHECK-NEXT: and %s1, %s1, (32)0 1201; CHECK-NEXT: lea.sl %s1, gv_i1@hi(, %s1) 1202; CHECK-NEXT: and %s2, 3, %s1 1203; CHECK-NEXT: sla.w.sx %s3, %s2, 3 1204; CHECK-NEXT: sla.w.sx %s0, %s0, %s3 1205; CHECK-NEXT: and %s1, -4, %s1 1206; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 1207; CHECK-NEXT: ts1am.w %s0, (%s1), %s2 1208; CHECK-NEXT: and %s0, %s0, (32)0 1209; CHECK-NEXT: srl %s0, %s0, %s3 1210; CHECK-NEXT: and %s0, 1, %s0 1211; CHECK-NEXT: b.l.t (, %s10) 1212 %2 = zext i1 %0 to i8 1213 %3 = atomicrmw xchg ptr @gv_i1, i8 %2 monotonic 1214 %4 = and i8 %3, 1 1215 %5 = icmp ne i8 %4, 0 1216 ret i1 %5 1217} 1218 1219; Function Attrs: nofree norecurse nounwind mustprogress 1220define signext i8 @_Z25atomic_swap_relaxed_gv_i8c(i8 signext %0) { 1221; CHECK-LABEL: _Z25atomic_swap_relaxed_gv_i8c: 1222; CHECK: # %bb.0: 1223; CHECK-NEXT: lea %s1, gv_i8@lo 1224; CHECK-NEXT: and %s1, %s1, (32)0 1225; CHECK-NEXT: lea.sl %s1, gv_i8@hi(, %s1) 1226; CHECK-NEXT: and %s2, 3, %s1 1227; CHECK-NEXT: sla.w.sx %s3, %s2, 3 1228; CHECK-NEXT: sla.w.sx %s0, %s0, %s3 1229; CHECK-NEXT: and %s1, -4, %s1 1230; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 1231; CHECK-NEXT: ts1am.w %s0, (%s1), %s2 1232; CHECK-NEXT: and %s0, %s0, (32)0 1233; CHECK-NEXT: srl %s0, %s0, %s3 1234; CHECK-NEXT: sll %s0, %s0, 56 1235; CHECK-NEXT: sra.l %s0, %s0, 56 1236; CHECK-NEXT: b.l.t (, %s10) 1237 %2 = atomicrmw xchg ptr @gv_i8, i8 %0 monotonic 1238 ret i8 %2 1239} 1240 1241; Function Attrs: nofree norecurse nounwind mustprogress 1242define zeroext i8 @_Z25atomic_swap_relaxed_gv_u8h(i8 zeroext %0) { 1243; CHECK-LABEL: _Z25atomic_swap_relaxed_gv_u8h: 1244; CHECK: # %bb.0: 1245; CHECK-NEXT: lea %s1, gv_u8@lo 1246; CHECK-NEXT: and %s1, %s1, (32)0 1247; CHECK-NEXT: lea.sl %s1, gv_u8@hi(, %s1) 1248; CHECK-NEXT: and %s2, 3, %s1 1249; CHECK-NEXT: sla.w.sx %s3, %s2, 3 1250; CHECK-NEXT: sla.w.sx %s0, %s0, %s3 1251; CHECK-NEXT: and %s1, -4, %s1 1252; CHECK-NEXT: sla.w.sx %s2, (63)0, %s2 1253; CHECK-NEXT: ts1am.w %s0, (%s1), %s2 1254; CHECK-NEXT: and %s0, %s0, (32)0 1255; CHECK-NEXT: srl %s0, %s0, %s3 1256; CHECK-NEXT: and %s0, %s0, (56)0 1257; CHECK-NEXT: b.l.t (, %s10) 1258 %2 = atomicrmw xchg ptr @gv_u8, i8 %0 monotonic 1259 ret i8 %2 1260} 1261 1262; Function Attrs: nofree norecurse nounwind mustprogress 1263define signext i16 @_Z26atomic_swap_relaxed_gv_i16s(i16 signext %0) { 1264; CHECK-LABEL: _Z26atomic_swap_relaxed_gv_i16s: 1265; CHECK: # %bb.0: 1266; CHECK-NEXT: lea %s1, gv_i16@lo 1267; CHECK-NEXT: and %s1, %s1, (32)0 1268; CHECK-NEXT: lea.sl %s1, gv_i16@hi(, %s1) 1269; CHECK-NEXT: and %s2, 3, %s1 1270; CHECK-NEXT: sla.w.sx %s3, %s2, 3 1271; CHECK-NEXT: sla.w.sx %s0, %s0, %s3 1272; CHECK-NEXT: and %s1, -4, %s1 1273; CHECK-NEXT: sla.w.sx %s2, (62)0, %s2 1274; CHECK-NEXT: ts1am.w %s0, (%s1), %s2 1275; CHECK-NEXT: and %s0, %s0, (32)0 1276; CHECK-NEXT: srl %s0, %s0, %s3 1277; CHECK-NEXT: sll %s0, %s0, 48 1278; CHECK-NEXT: sra.l %s0, %s0, 48 1279; CHECK-NEXT: b.l.t (, %s10) 1280 %2 = atomicrmw xchg ptr @gv_i16, i16 %0 monotonic 1281 ret i16 %2 1282} 1283 1284; Function Attrs: nofree norecurse nounwind mustprogress 1285define zeroext i16 @_Z26atomic_swap_relaxed_gv_u16t(i16 zeroext %0) { 1286; CHECK-LABEL: _Z26atomic_swap_relaxed_gv_u16t: 1287; CHECK: # %bb.0: 1288; CHECK-NEXT: lea %s1, gv_u16@lo 1289; CHECK-NEXT: and %s1, %s1, (32)0 1290; CHECK-NEXT: lea.sl %s1, gv_u16@hi(, %s1) 1291; CHECK-NEXT: and %s2, 3, %s1 1292; CHECK-NEXT: sla.w.sx %s3, %s2, 3 1293; CHECK-NEXT: sla.w.sx %s0, %s0, %s3 1294; CHECK-NEXT: and %s1, -4, %s1 1295; CHECK-NEXT: sla.w.sx %s2, (62)0, %s2 1296; CHECK-NEXT: ts1am.w %s0, (%s1), %s2 1297; CHECK-NEXT: and %s0, %s0, (32)0 1298; CHECK-NEXT: srl %s0, %s0, %s3 1299; CHECK-NEXT: and %s0, %s0, (48)0 1300; CHECK-NEXT: b.l.t (, %s10) 1301 %2 = atomicrmw xchg ptr @gv_u16, i16 %0 monotonic 1302 ret i16 %2 1303} 1304 1305; Function Attrs: nofree norecurse nounwind mustprogress 1306define signext i32 @_Z26atomic_swap_relaxed_gv_i32i(i32 signext %0) { 1307; CHECK-LABEL: _Z26atomic_swap_relaxed_gv_i32i: 1308; CHECK: # %bb.0: 1309; CHECK-NEXT: lea %s1, gv_i32@lo 1310; CHECK-NEXT: and %s1, %s1, (32)0 1311; CHECK-NEXT: lea.sl %s1, gv_i32@hi(, %s1) 1312; CHECK-NEXT: ts1am.w %s0, (%s1), 15 1313; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 1314; CHECK-NEXT: b.l.t (, %s10) 1315 %2 = atomicrmw xchg ptr @gv_i32, i32 %0 monotonic 1316 ret i32 %2 1317} 1318 1319; Function Attrs: nofree norecurse nounwind mustprogress 1320define zeroext i32 @_Z26atomic_swap_relaxed_gv_u32j(i32 zeroext %0) { 1321; CHECK-LABEL: _Z26atomic_swap_relaxed_gv_u32j: 1322; CHECK: # %bb.0: 1323; CHECK-NEXT: lea %s1, gv_u32@lo 1324; CHECK-NEXT: and %s1, %s1, (32)0 1325; CHECK-NEXT: lea.sl %s1, gv_u32@hi(, %s1) 1326; CHECK-NEXT: ts1am.w %s0, (%s1), 15 1327; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 1328; CHECK-NEXT: b.l.t (, %s10) 1329 %2 = atomicrmw xchg ptr @gv_u32, i32 %0 monotonic 1330 ret i32 %2 1331} 1332 1333; Function Attrs: nofree norecurse nounwind mustprogress 1334define i64 @_Z26atomic_swap_relaxed_gv_i64l(i64 %0) { 1335; CHECK-LABEL: _Z26atomic_swap_relaxed_gv_i64l: 1336; CHECK: # %bb.0: 1337; CHECK-NEXT: lea %s1, gv_i64@lo 1338; CHECK-NEXT: and %s1, %s1, (32)0 1339; CHECK-NEXT: lea.sl %s1, gv_i64@hi(, %s1) 1340; CHECK-NEXT: lea %s2, 255 1341; CHECK-NEXT: ts1am.l %s0, (%s1), %s2 1342; CHECK-NEXT: b.l.t (, %s10) 1343 %2 = atomicrmw xchg ptr @gv_i64, i64 %0 monotonic 1344 ret i64 %2 1345} 1346 1347; Function Attrs: nofree norecurse nounwind mustprogress 1348define i64 @_Z26atomic_swap_relaxed_gv_u64m(i64 %0) { 1349; CHECK-LABEL: _Z26atomic_swap_relaxed_gv_u64m: 1350; CHECK: # %bb.0: 1351; CHECK-NEXT: lea %s1, gv_u64@lo 1352; CHECK-NEXT: and %s1, %s1, (32)0 1353; CHECK-NEXT: lea.sl %s1, gv_u64@hi(, %s1) 1354; CHECK-NEXT: lea %s2, 255 1355; CHECK-NEXT: ts1am.l %s0, (%s1), %s2 1356; CHECK-NEXT: b.l.t (, %s10) 1357 %2 = atomicrmw xchg ptr @gv_u64, i64 %0 monotonic 1358 ret i64 %2 1359} 1360 1361; Function Attrs: nounwind mustprogress 1362define i128 @_Z27atomic_swap_relaxed_gv_i128n(i128 %0) { 1363; CHECK-LABEL: _Z27atomic_swap_relaxed_gv_i128n: 1364; CHECK: # %bb.0: 1365; CHECK-NEXT: st %s9, (, %s11) 1366; CHECK-NEXT: st %s10, 8(, %s11) 1367; CHECK-NEXT: or %s9, 0, %s11 1368; CHECK-NEXT: lea %s11, -272(, %s11) 1369; CHECK-NEXT: brge.l.t %s11, %s8, .LBB53_2 1370; CHECK-NEXT: # %bb.1: 1371; CHECK-NEXT: ld %s61, 24(, %s14) 1372; CHECK-NEXT: or %s62, 0, %s0 1373; CHECK-NEXT: lea %s63, 315 1374; CHECK-NEXT: shm.l %s63, (%s61) 1375; CHECK-NEXT: shm.l %s8, 8(%s61) 1376; CHECK-NEXT: shm.l %s11, 16(%s61) 1377; CHECK-NEXT: monc 1378; CHECK-NEXT: or %s0, 0, %s62 1379; CHECK-NEXT: .LBB53_2: 1380; CHECK-NEXT: st %s1, 264(, %s11) 1381; CHECK-NEXT: st %s0, 256(, %s11) 1382; CHECK-NEXT: lea %s0, __atomic_exchange@lo 1383; CHECK-NEXT: and %s0, %s0, (32)0 1384; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 1385; CHECK-NEXT: lea %s0, gv_i128@lo 1386; CHECK-NEXT: and %s0, %s0, (32)0 1387; CHECK-NEXT: lea.sl %s1, gv_i128@hi(, %s0) 1388; CHECK-NEXT: lea %s2, 256(, %s11) 1389; CHECK-NEXT: lea %s3, 240(, %s11) 1390; CHECK-NEXT: or %s0, 16, (0)1 1391; CHECK-NEXT: or %s4, 0, (0)1 1392; CHECK-NEXT: bsic %s10, (, %s12) 1393; CHECK-NEXT: ld %s1, 248(, %s11) 1394; CHECK-NEXT: ld %s0, 240(, %s11) 1395; CHECK-NEXT: or %s11, 0, %s9 1396; CHECK-NEXT: ld %s10, 8(, %s11) 1397; CHECK-NEXT: ld %s9, (, %s11) 1398; CHECK-NEXT: b.l.t (, %s10) 1399 %2 = alloca i128, align 16 1400 %3 = alloca i128, align 16 1401 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2) 1402 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 1403 store i128 %0, ptr %2, align 16, !tbaa !2 1404 call void @__atomic_exchange(i64 16, ptr nonnull @gv_i128, ptr nonnull %2, ptr nonnull %3, i32 signext 0) 1405 %4 = load i128, ptr %3, align 16, !tbaa !2 1406 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %2) 1407 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 1408 ret i128 %4 1409} 1410 1411; Function Attrs: nounwind mustprogress 1412define i128 @_Z27atomic_swap_relaxed_gv_u128o(i128 %0) { 1413; CHECK-LABEL: _Z27atomic_swap_relaxed_gv_u128o: 1414; CHECK: # %bb.0: 1415; CHECK-NEXT: st %s9, (, %s11) 1416; CHECK-NEXT: st %s10, 8(, %s11) 1417; CHECK-NEXT: or %s9, 0, %s11 1418; CHECK-NEXT: lea %s11, -272(, %s11) 1419; CHECK-NEXT: brge.l.t %s11, %s8, .LBB54_2 1420; CHECK-NEXT: # %bb.1: 1421; CHECK-NEXT: ld %s61, 24(, %s14) 1422; CHECK-NEXT: or %s62, 0, %s0 1423; CHECK-NEXT: lea %s63, 315 1424; CHECK-NEXT: shm.l %s63, (%s61) 1425; CHECK-NEXT: shm.l %s8, 8(%s61) 1426; CHECK-NEXT: shm.l %s11, 16(%s61) 1427; CHECK-NEXT: monc 1428; CHECK-NEXT: or %s0, 0, %s62 1429; CHECK-NEXT: .LBB54_2: 1430; CHECK-NEXT: st %s1, 264(, %s11) 1431; CHECK-NEXT: st %s0, 256(, %s11) 1432; CHECK-NEXT: lea %s0, __atomic_exchange@lo 1433; CHECK-NEXT: and %s0, %s0, (32)0 1434; CHECK-NEXT: lea.sl %s12, __atomic_exchange@hi(, %s0) 1435; CHECK-NEXT: lea %s0, gv_u128@lo 1436; CHECK-NEXT: and %s0, %s0, (32)0 1437; CHECK-NEXT: lea.sl %s1, gv_u128@hi(, %s0) 1438; CHECK-NEXT: lea %s2, 256(, %s11) 1439; CHECK-NEXT: lea %s3, 240(, %s11) 1440; CHECK-NEXT: or %s0, 16, (0)1 1441; CHECK-NEXT: or %s4, 0, (0)1 1442; CHECK-NEXT: bsic %s10, (, %s12) 1443; CHECK-NEXT: ld %s1, 248(, %s11) 1444; CHECK-NEXT: ld %s0, 240(, %s11) 1445; CHECK-NEXT: or %s11, 0, %s9 1446; CHECK-NEXT: ld %s10, 8(, %s11) 1447; CHECK-NEXT: ld %s9, (, %s11) 1448; CHECK-NEXT: b.l.t (, %s10) 1449 %2 = alloca i128, align 16 1450 %3 = alloca i128, align 16 1451 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2) 1452 call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) 1453 store i128 %0, ptr %2, align 16, !tbaa !2 1454 call void @__atomic_exchange(i64 16, ptr nonnull @gv_u128, ptr nonnull %2, ptr nonnull %3, i32 signext 0) 1455 %4 = load i128, ptr %3, align 16, !tbaa !2 1456 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %2) 1457 call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) 1458 ret i128 %4 1459} 1460 1461; Function Attrs: nounwind willreturn 1462declare void @__atomic_exchange(i64, ptr, ptr, ptr, i32) 1463 1464!2 = !{!3, !3, i64 0} 1465!3 = !{!"__int128", !4, i64 0} 1466!4 = !{!"omnipotent char", !5, i64 0} 1467!5 = !{!"Simple C++ TBAA"} 1468