xref: /llvm-project/llvm/test/CodeGen/VE/Packed/vp_srl.ll (revision 5240e0b891fc4bf69d362199f70c94c28a7b9465) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
3
4declare <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
5
6define fastcc <512 x i32> @test_vp_lshr_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
7; CHECK-LABEL: test_vp_lshr_v512i32_vv:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    adds.w.sx %s0, 1, %s0
10; CHECK-NEXT:    and %s0, %s0, (32)0
11; CHECK-NEXT:    srl %s0, %s0, 1
12; CHECK-NEXT:    lvl %s0
13; CHECK-NEXT:    pvsrl %v0, %v0, %v1, %vm2
14; CHECK-NEXT:    b.l.t (, %s10)
15  %r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
16  ret <512 x i32> %r0
17}
18
19define fastcc <512 x i32> @test_vp_lshr_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
20; CHECK-LABEL: test_vp_lshr_v512i32_rv:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    and %s0, %s0, (32)0
23; CHECK-NEXT:    sll %s2, %s0, 32
24; CHECK-NEXT:    and %s0, %s0, (32)0
25; CHECK-NEXT:    or %s0, %s0, %s2
26; CHECK-NEXT:    lea %s2, 256
27; CHECK-NEXT:    lvl %s2
28; CHECK-NEXT:    vbrd %v1, %s0
29; CHECK-NEXT:    adds.w.sx %s0, 1, %s1
30; CHECK-NEXT:    and %s0, %s0, (32)0
31; CHECK-NEXT:    srl %s0, %s0, 1
32; CHECK-NEXT:    lvl %s0
33; CHECK-NEXT:    pvsrl %v0, %v1, %v0, %vm2
34; CHECK-NEXT:    b.l.t (, %s10)
35  %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
36  %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
37  %r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
38  ret <512 x i32> %r0
39}
40
41define fastcc <512 x i32> @test_vp_lshr_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
42; CHECK-LABEL: test_vp_lshr_v512i32_vr:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    and %s0, %s0, (32)0
45; CHECK-NEXT:    sll %s2, %s0, 32
46; CHECK-NEXT:    and %s0, %s0, (32)0
47; CHECK-NEXT:    or %s0, %s0, %s2
48; CHECK-NEXT:    adds.w.sx %s1, 1, %s1
49; CHECK-NEXT:    and %s1, %s1, (32)0
50; CHECK-NEXT:    srl %s1, %s1, 1
51; CHECK-NEXT:    lvl %s1
52; CHECK-NEXT:    pvsrl %v0, %v0, %s0, %vm2
53; CHECK-NEXT:    b.l.t (, %s10)
54  %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
55  %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
56  %r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
57  ret <512 x i32> %r0
58}
59