1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK-DSP 3; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP 4; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP 5; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP 6; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP 7 8define i32 @test1(i32 %x) { 9; CHECK-DSP-LABEL: test1: 10; CHECK-DSP: @ %bb.0: 11; CHECK-DSP-NEXT: uxtb16 r0, r0 12; CHECK-DSP-NEXT: bx lr 13; 14; CHECK-NO-DSP-LABEL: test1: 15; CHECK-NO-DSP: @ %bb.0: 16; CHECK-NO-DSP-NEXT: bic r0, r0, #-16711936 17; CHECK-NO-DSP-NEXT: bx lr 18 %tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1] 19 ret i32 %tmp1 20} 21 22; PR7503 23define i32 @test2(i32 %x) { 24; CHECK-DSP-LABEL: test2: 25; CHECK-DSP: @ %bb.0: 26; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #8 27; CHECK-DSP-NEXT: bx lr 28; 29; CHECK-NO-DSP-LABEL: test2: 30; CHECK-NO-DSP: @ %bb.0: 31; CHECK-NO-DSP-NEXT: mov.w r1, #16711935 32; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, lsr #8 33; CHECK-NO-DSP-NEXT: bx lr 34 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] 35 %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] 36 ret i32 %tmp2 37} 38 39define i32 @test3(i32 %x) { 40; CHECK-DSP-LABEL: test3: 41; CHECK-DSP: @ %bb.0: 42; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #8 43; CHECK-DSP-NEXT: bx lr 44; 45; CHECK-NO-DSP-LABEL: test3: 46; CHECK-NO-DSP: @ %bb.0: 47; CHECK-NO-DSP-NEXT: mov.w r1, #16711935 48; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, lsr #8 49; CHECK-NO-DSP-NEXT: bx lr 50 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] 51 %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] 52 ret i32 %tmp2 53} 54 55define i32 @test4(i32 %x) { 56; CHECK-DSP-LABEL: test4: 57; CHECK-DSP: @ %bb.0: 58; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #8 59; CHECK-DSP-NEXT: bx lr 60; 61; CHECK-NO-DSP-LABEL: test4: 62; CHECK-NO-DSP: @ %bb.0: 63; CHECK-NO-DSP-NEXT: mov.w r1, #16711935 64; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, lsr #8 65; CHECK-NO-DSP-NEXT: bx lr 66 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] 67 %tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] 68 ret i32 %tmp6 69} 70 71define i32 @test5(i32 %x) { 72; CHECK-DSP-LABEL: test5: 73; CHECK-DSP: @ %bb.0: 74; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #8 75; CHECK-DSP-NEXT: bx lr 76; 77; CHECK-NO-DSP-LABEL: test5: 78; CHECK-NO-DSP: @ %bb.0: 79; CHECK-NO-DSP-NEXT: mov.w r1, #16711935 80; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, lsr #8 81; CHECK-NO-DSP-NEXT: bx lr 82 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] 83 %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] 84 ret i32 %tmp2 85} 86 87define i32 @test6(i32 %x) { 88; CHECK-DSP-LABEL: test6: 89; CHECK-DSP: @ %bb.0: 90; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #16 91; CHECK-DSP-NEXT: bx lr 92; 93; CHECK-NO-DSP-LABEL: test6: 94; CHECK-NO-DSP: @ %bb.0: 95; CHECK-NO-DSP-NEXT: mov.w r1, #16711935 96; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, ror #16 97; CHECK-NO-DSP-NEXT: bx lr 98 %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1] 99 %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1] 100 %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1] 101 %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1] 102 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1] 103 ret i32 %tmp6 104} 105 106define i32 @test7(i32 %x) { 107; CHECK-DSP-LABEL: test7: 108; CHECK-DSP: @ %bb.0: 109; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #16 110; CHECK-DSP-NEXT: bx lr 111; 112; CHECK-NO-DSP-LABEL: test7: 113; CHECK-NO-DSP: @ %bb.0: 114; CHECK-NO-DSP-NEXT: mov.w r1, #16711935 115; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, ror #16 116; CHECK-NO-DSP-NEXT: bx lr 117 %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1] 118 %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1] 119 %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1] 120 %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1] 121 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1] 122 ret i32 %tmp6 123} 124 125define i32 @test8(i32 %x) { 126; CHECK-DSP-LABEL: test8: 127; CHECK-DSP: @ %bb.0: 128; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #24 129; CHECK-DSP-NEXT: bx lr 130; 131; CHECK-NO-DSP-LABEL: test8: 132; CHECK-NO-DSP: @ %bb.0: 133; CHECK-NO-DSP-NEXT: mov.w r1, #16711935 134; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, ror #24 135; CHECK-NO-DSP-NEXT: bx lr 136 %tmp1 = shl i32 %x, 8 ; <i32> [#uses=1] 137 %tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1] 138 %tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1] 139 %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1] 140 ret i32 %tmp6 141} 142 143define i32 @test9(i32 %x) { 144; CHECK-DSP-LABEL: test9: 145; CHECK-DSP: @ %bb.0: 146; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #24 147; CHECK-DSP-NEXT: bx lr 148; 149; CHECK-NO-DSP-LABEL: test9: 150; CHECK-NO-DSP: @ %bb.0: 151; CHECK-NO-DSP-NEXT: mov.w r1, #16711935 152; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, ror #24 153; CHECK-NO-DSP-NEXT: bx lr 154 %tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1] 155 %tmp4 = shl i32 %x, 8 ; <i32> [#uses=1] 156 %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1] 157 %tmp6 = or i32 %tmp5, %tmp1 ; <i32> [#uses=1] 158 ret i32 %tmp6 159} 160 161; FIXME: Failed to match uxtb16 162define i32 @test10(i32 %p0) { 163; CHECK-DSP-LABEL: test10: 164; CHECK-DSP: @ %bb.0: 165; CHECK-DSP-NEXT: mov.w r1, #16253176 166; CHECK-DSP-NEXT: mov.w r2, #458759 167; CHECK-DSP-NEXT: and.w r1, r1, r0, lsr #7 168; CHECK-DSP-NEXT: and.w r0, r2, r0, lsr #12 169; CHECK-DSP-NEXT: add r0, r1 170; CHECK-DSP-NEXT: bx lr 171; 172; CHECK-NO-DSP-LABEL: test10: 173; CHECK-NO-DSP: @ %bb.0: 174; CHECK-NO-DSP-NEXT: mov.w r1, #16253176 175; CHECK-NO-DSP-NEXT: mov.w r2, #458759 176; CHECK-NO-DSP-NEXT: and.w r1, r1, r0, lsr #7 177; CHECK-NO-DSP-NEXT: and.w r0, r2, r0, lsr #12 178; CHECK-NO-DSP-NEXT: add r0, r1 179; CHECK-NO-DSP-NEXT: bx lr 180 %tmp1 = lshr i32 %p0, 7 181 %tmp2 = and i32 %tmp1, 16253176 182 %tmp4 = lshr i32 %p0, 12 183 %tmp5 = and i32 %tmp4, 458759 184 %tmp7 = or i32 %tmp5, %tmp2 185 ret i32 %tmp7 186} 187 188define i32 @test11(i32 %p0) { 189; CHECK-DSP-LABEL: test11: 190; CHECK-DSP: @ %bb.0: 191; CHECK-DSP-NEXT: and r0, r0, #3 192; CHECK-DSP-NEXT: mov.w r1, #65537 193; CHECK-DSP-NEXT: lsl.w r0, r1, r0 194; CHECK-DSP-NEXT: lsrs r0, r0, #1 195; CHECK-DSP-NEXT: uxtb16 r0, r0 196; CHECK-DSP-NEXT: bx lr 197; 198; CHECK-NO-DSP-LABEL: test11: 199; CHECK-NO-DSP: @ %bb.0: 200; CHECK-NO-DSP-NEXT: and r0, r0, #3 201; CHECK-NO-DSP-NEXT: mov.w r1, #65537 202; CHECK-NO-DSP-NEXT: lsl.w r0, r1, r0 203; CHECK-NO-DSP-NEXT: mov.w r1, #458759 204; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, lsr #1 205; CHECK-NO-DSP-NEXT: bx lr 206 %p = and i32 %p0, 3 207 %a = shl i32 65537, %p 208 %b = lshr i32 %a, 1 209 %tmp7 = and i32 %b, 458759 210 ret i32 %tmp7 211} 212 213