1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-DSP 3; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DSP 4; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP 5; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-NO-DSP 6; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP 7; rdar://11318438 8 9define zeroext i8 @test1(i32 %A.u) { 10; CHECK-LABEL: test1: 11; CHECK: @ %bb.0: 12; CHECK-NEXT: uxtb r0, r0 13; CHECK-NEXT: bx lr 14 %B.u = trunc i32 %A.u to i8 15 ret i8 %B.u 16} 17 18define zeroext i32 @test2(i32 %A.u, i32 %B.u) { 19; CHECK-DSP-LABEL: test2: 20; CHECK-DSP: @ %bb.0: 21; CHECK-DSP-NEXT: uxtab r0, r0, r1 22; CHECK-DSP-NEXT: bx lr 23; 24; CHECK-NO-DSP-LABEL: test2: 25; CHECK-NO-DSP: @ %bb.0: 26; CHECK-NO-DSP-NEXT: uxtb r1, r1 27; CHECK-NO-DSP-NEXT: add r0, r1 28; CHECK-NO-DSP-NEXT: bx lr 29 %C.u = trunc i32 %B.u to i8 30 %D.u = zext i8 %C.u to i32 31 %E.u = add i32 %A.u, %D.u 32 ret i32 %E.u 33} 34 35define zeroext i32 @test3(i32 %A.u) { 36; CHECK-LABEL: test3: 37; CHECK: @ %bb.0: 38; CHECK-NEXT: ubfx r0, r0, #8, #16 39; CHECK-NEXT: bx lr 40 %B.u = lshr i32 %A.u, 8 41 %C.u = shl i32 %A.u, 24 42 %D.u = or i32 %B.u, %C.u 43 %E.u = trunc i32 %D.u to i16 44 %F.u = zext i16 %E.u to i32 45 ret i32 %F.u 46} 47 48define i32 @test4(i32 %A, i32 %X) { 49; CHECK-DSP-LABEL: test4: 50; CHECK-DSP: @ %bb.0: 51; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #16 52; CHECK-DSP-NEXT: bx lr 53; 54; CHECK-NO-DSP-LABEL: test4: 55; CHECK-NO-DSP: @ %bb.0: 56; CHECK-NO-DSP-NEXT: ubfx r1, r1, #16, #8 57; CHECK-NO-DSP-NEXT: add r0, r1 58; CHECK-NO-DSP-NEXT: bx lr 59 %X.hi = lshr i32 %X, 16 60 %X.trunc = trunc i32 %X.hi to i8 61 %addend = zext i8 %X.trunc to i32 62 %sum = add i32 %A, %addend 63 ret i32 %sum 64} 65 66define i32 @test5(i32 %A, i32 %X) { 67; CHECK-DSP-LABEL: test5: 68; CHECK-DSP: @ %bb.0: 69; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #8 70; CHECK-DSP-NEXT: bx lr 71; 72; CHECK-NO-DSP-LABEL: test5: 73; CHECK-NO-DSP: @ %bb.0: 74; CHECK-NO-DSP-NEXT: ubfx r1, r1, #8, #16 75; CHECK-NO-DSP-NEXT: add r0, r1 76; CHECK-NO-DSP-NEXT: bx lr 77 %X.hi = lshr i32 %X, 8 78 %X.trunc = trunc i32 %X.hi to i16 79 %addend = zext i16 %X.trunc to i32 80 %sum = add i32 %A, %addend 81 ret i32 %sum 82} 83 84define i32 @test6(i32 %A, i32 %X) { 85; CHECK-DSP-LABEL: test6: 86; CHECK-DSP: @ %bb.0: 87; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #8 88; CHECK-DSP-NEXT: bx lr 89; 90; CHECK-NO-DSP-LABEL: test6: 91; CHECK-NO-DSP: @ %bb.0: 92; CHECK-NO-DSP-NEXT: ubfx r1, r1, #8, #8 93; CHECK-NO-DSP-NEXT: add r0, r1 94; CHECK-NO-DSP-NEXT: bx lr 95 %X.hi = lshr i32 %X, 8 96 %X.trunc = trunc i32 %X.hi to i8 97 %addend = zext i8 %X.trunc to i32 98 %sum = add i32 %A, %addend 99 ret i32 %sum 100} 101 102define i32 @test7(i32 %A, i32 %X) { 103; CHECK-DSP-LABEL: test7: 104; CHECK-DSP: @ %bb.0: 105; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24 106; CHECK-DSP-NEXT: bx lr 107; 108; CHECK-NO-DSP-LABEL: test7: 109; CHECK-NO-DSP: @ %bb.0: 110; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24 111; CHECK-NO-DSP-NEXT: uxth r1, r1 112; CHECK-NO-DSP-NEXT: add r0, r1 113; CHECK-NO-DSP-NEXT: bx lr 114 %lshr = lshr i32 %X, 24 115 %shl = shl i32 %X, 8 116 %or = or i32 %lshr, %shl 117 %trunc = trunc i32 %or to i16 118 %zext = zext i16 %trunc to i32 119 %add = add i32 %A, %zext 120 ret i32 %add 121} 122 123define i32 @test8(i32 %A, i32 %X) { 124; CHECK-DSP-LABEL: test8: 125; CHECK-DSP: @ %bb.0: 126; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24 127; CHECK-DSP-NEXT: bx lr 128; 129; CHECK-NO-DSP-LABEL: test8: 130; CHECK-NO-DSP: @ %bb.0: 131; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24 132; CHECK-NO-DSP-NEXT: uxth r1, r1 133; CHECK-NO-DSP-NEXT: add r0, r1 134; CHECK-NO-DSP-NEXT: bx lr 135 %lshr = lshr i32 %X, 24 136 %shl = shl i32 %X, 8 137 %or = or i32 %lshr, %shl 138 %and = and i32 %or, 65535 139 %add = add i32 %A, %and 140 ret i32 %add 141} 142