xref: /llvm-project/llvm/test/CodeGen/Thumb2/thumb2-teq2.ll (revision 9db1eb13b64b5062e8bc34912c44d5175c26bf78) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
3
4; These tests would be improved by 'movs r0, #0' being rematerialized below the
5; tst as 'mov.w r0, #0'.
6
7define i32 @f2(i32 %a, i32 %b) {
8; CHECK-LABEL: f2:
9; CHECK:       @ %bb.0:
10; CHECK-NEXT:    movs r2, #24
11; CHECK-NEXT:    eors r0, r1
12; CHECK-NEXT:    it eq
13; CHECK-NEXT:    moveq r2, #42
14; CHECK-NEXT:    mov r0, r2
15; CHECK-NEXT:    bx lr
16    %tmp = xor i32 %a, %b
17    %tmp1 = icmp eq i32 %tmp, 0
18    %ret = select i1 %tmp1, i32 42, i32 24
19    ret i32 %ret
20}
21
22define i32 @f4(i32 %a, i32 %b) {
23; CHECK-LABEL: f4:
24; CHECK:       @ %bb.0:
25; CHECK-NEXT:    movs r2, #24
26; CHECK-NEXT:    eors r0, r1
27; CHECK-NEXT:    it eq
28; CHECK-NEXT:    moveq r2, #42
29; CHECK-NEXT:    mov r0, r2
30; CHECK-NEXT:    bx lr
31    %tmp = xor i32 %a, %b
32    %tmp1 = icmp eq i32 0, %tmp
33    %ret = select i1 %tmp1, i32 42, i32 24
34    ret i32 %ret
35}
36
37define i32 @f6(i32 %a, i32 %b) {
38; CHECK-LABEL: f6:
39; CHECK:       @ %bb.0:
40; CHECK-NEXT:    movs r2, #24
41; CHECK-NEXT:    teq.w r0, r1, lsl #5
42; CHECK-NEXT:    it eq
43; CHECK-NEXT:    moveq r2, #42
44; CHECK-NEXT:    mov r0, r2
45; CHECK-NEXT:    bx lr
46    %tmp = shl i32 %b, 5
47    %tmp1 = xor i32 %a, %tmp
48    %tmp2 = icmp eq i32 %tmp1, 0
49    %ret = select i1 %tmp2, i32 42, i32 24
50    ret i32 %ret
51}
52
53define i32 @f7(i32 %a, i32 %b) {
54; CHECK-LABEL: f7:
55; CHECK:       @ %bb.0:
56; CHECK-NEXT:    movs r2, #24
57; CHECK-NEXT:    teq.w r0, r1, lsr #6
58; CHECK-NEXT:    it eq
59; CHECK-NEXT:    moveq r2, #42
60; CHECK-NEXT:    mov r0, r2
61; CHECK-NEXT:    bx lr
62    %tmp = lshr i32 %b, 6
63    %tmp1 = xor i32 %a, %tmp
64    %tmp2 = icmp eq i32 %tmp1, 0
65    %ret = select i1 %tmp2, i32 42, i32 24
66    ret i32 %ret
67}
68
69define i32 @f8(i32 %a, i32 %b) {
70; CHECK-LABEL: f8:
71; CHECK:       @ %bb.0:
72; CHECK-NEXT:    movs r2, #24
73; CHECK-NEXT:    teq.w r0, r1, asr #7
74; CHECK-NEXT:    it eq
75; CHECK-NEXT:    moveq r2, #42
76; CHECK-NEXT:    mov r0, r2
77; CHECK-NEXT:    bx lr
78    %tmp = ashr i32 %b, 7
79    %tmp1 = xor i32 %a, %tmp
80    %tmp2 = icmp eq i32 %tmp1, 0
81    %ret = select i1 %tmp2, i32 42, i32 24
82    ret i32 %ret
83}
84
85define i32 @f9(i32 %a, i32 %b) {
86; CHECK-LABEL: f9:
87; CHECK:       @ %bb.0:
88; CHECK-NEXT:    movs r1, #24
89; CHECK-NEXT:    teq.w r0, r0, ror #8
90; CHECK-NEXT:    it eq
91; CHECK-NEXT:    moveq r1, #42
92; CHECK-NEXT:    mov r0, r1
93; CHECK-NEXT:    bx lr
94    %l8 = shl i32 %a, 24
95    %r8 = lshr i32 %a, 8
96    %tmp = or i32 %l8, %r8
97    %tmp1 = xor i32 %a, %tmp
98    %tmp2 = icmp eq i32 %tmp1, 0
99    %ret = select i1 %tmp2, i32 42, i32 24
100    ret i32 %ret
101}
102