1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s 3 4; These tests would be improved by 'movs r0, #0' being rematerialized below the 5; test as 'mov.w r0, #0'. 6 7; 0x000000bb = 187 8define i32 @f2(i32 %a) { 9; CHECK-LABEL: f2: 10; CHECK: @ %bb.0: 11; CHECK-NEXT: movs r1, #24 12; CHECK-NEXT: cmp r0, #187 13; CHECK-NEXT: it eq 14; CHECK-NEXT: moveq r1, #42 15; CHECK-NEXT: mov r0, r1 16; CHECK-NEXT: bx lr 17 %tmp = xor i32 %a, 187 18 %tmp1 = icmp eq i32 0, %tmp 19 %ret = select i1 %tmp1, i32 42, i32 24 20 ret i32 %ret 21} 22 23; 0x00aa00aa = 11141290 24define i32 @f3(i32 %a) { 25; CHECK-LABEL: f3: 26; CHECK: @ %bb.0: 27; CHECK-NEXT: movs r1, #24 28; CHECK-NEXT: cmp.w r0, #11141290 29; CHECK-NEXT: it eq 30; CHECK-NEXT: moveq r1, #42 31; CHECK-NEXT: mov r0, r1 32; CHECK-NEXT: bx lr 33 %tmp = xor i32 %a, 11141290 34 %tmp1 = icmp eq i32 %tmp, 0 35 %ret = select i1 %tmp1, i32 42, i32 24 36 ret i32 %ret 37} 38 39; 0xcc00cc00 = 3422604288 40define i32 @f6(i32 %a) { 41; CHECK-LABEL: f6: 42; CHECK: @ %bb.0: 43; CHECK-NEXT: movs r1, #24 44; CHECK-NEXT: cmp.w r0, #-872363008 45; CHECK-NEXT: it eq 46; CHECK-NEXT: moveq r1, #42 47; CHECK-NEXT: mov r0, r1 48; CHECK-NEXT: bx lr 49 %tmp = xor i32 %a, 3422604288 50 %tmp1 = icmp eq i32 0, %tmp 51 %ret = select i1 %tmp1, i32 42, i32 24 52 ret i32 %ret 53} 54 55; 0xdddddddd = 3722304989 56define i32 @f7(i32 %a) { 57; CHECK-LABEL: f7: 58; CHECK: @ %bb.0: 59; CHECK-NEXT: movs r1, #24 60; CHECK-NEXT: cmp.w r0, #-572662307 61; CHECK-NEXT: it eq 62; CHECK-NEXT: moveq r1, #42 63; CHECK-NEXT: mov r0, r1 64; CHECK-NEXT: bx lr 65 %tmp = xor i32 %a, 3722304989 66 %tmp1 = icmp eq i32 %tmp, 0 67 %ret = select i1 %tmp1, i32 42, i32 24 68 ret i32 %ret 69} 70 71; 0x00110000 = 1114112 72define i32 @f10(i32 %a) { 73; CHECK-LABEL: f10: 74; CHECK: @ %bb.0: 75; CHECK-NEXT: movs r1, #24 76; CHECK-NEXT: cmp.w r0, #1114112 77; CHECK-NEXT: it eq 78; CHECK-NEXT: moveq r1, #42 79; CHECK-NEXT: mov r0, r1 80; CHECK-NEXT: bx lr 81 %tmp = xor i32 %a, 1114112 82 %tmp1 = icmp eq i32 0, %tmp 83 %ret = select i1 %tmp1, i32 42, i32 24 84 ret i32 %ret 85} 86 87; 0x000000bb = 187 88define i1 @f12(i32 %a) { 89; CHECK-LABEL: f12: 90; CHECK: @ %bb.0: 91; CHECK-NEXT: subs r0, #187 92; CHECK-NEXT: clz r0, r0 93; CHECK-NEXT: lsrs r0, r0, #5 94; CHECK-NEXT: bx lr 95 %tmp = xor i32 %a, 187 96 %tmp1 = icmp eq i32 0, %tmp 97 ret i1 %tmp1 98} 99 100; 0x00aa00aa = 11141290 101define i1 @f13(i32 %a) { 102; CHECK-LABEL: f13: 103; CHECK: @ %bb.0: 104; CHECK-NEXT: sub.w r0, r0, #11141290 105; CHECK-NEXT: clz r0, r0 106; CHECK-NEXT: lsrs r0, r0, #5 107; CHECK-NEXT: bx lr 108 %tmp = xor i32 %a, 11141290 109 %tmp1 = icmp eq i32 %tmp, 0 110 ret i1 %tmp1 111} 112 113; 0xcc00cc00 = 3422604288 114define i1 @f16(i32 %a) { 115; CHECK-LABEL: f16: 116; CHECK: @ %bb.0: 117; CHECK-NEXT: sub.w r0, r0, #-872363008 118; CHECK-NEXT: clz r0, r0 119; CHECK-NEXT: lsrs r0, r0, #5 120; CHECK-NEXT: bx lr 121 %tmp = xor i32 %a, 3422604288 122 %tmp1 = icmp eq i32 0, %tmp 123 ret i1 %tmp1 124} 125 126; 0xdddddddd = 3722304989 127define i1 @f17(i32 %a) { 128; CHECK-LABEL: f17: 129; CHECK: @ %bb.0: 130; CHECK-NEXT: sub.w r0, r0, #-572662307 131; CHECK-NEXT: clz r0, r0 132; CHECK-NEXT: lsrs r0, r0, #5 133; CHECK-NEXT: bx lr 134 %tmp = xor i32 %a, 3722304989 135 %tmp1 = icmp eq i32 %tmp, 0 136 ret i1 %tmp1 137} 138 139; 0x00110000 = 1114112 140define i1 @f18(i32 %a) { 141; CHECK-LABEL: f18: 142; CHECK: @ %bb.0: 143; CHECK-NEXT: sub.w r0, r0, #1114112 144; CHECK-NEXT: clz r0, r0 145; CHECK-NEXT: lsrs r0, r0, #5 146; CHECK-NEXT: bx lr 147 %tmp = xor i32 %a, 1114112 148 %tmp1 = icmp eq i32 0, %tmp 149 ret i1 %tmp1 150} 151 152