1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-DSP 3; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DSP 4; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP 5; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-NO-DSP 6; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP 7 8define i32 @test0(i8 %A) { 9; CHECK-LABEL: test0: 10; CHECK: @ %bb.0: 11; CHECK-NEXT: sxtb r0, r0 12; CHECK-NEXT: bx lr 13 %B = sext i8 %A to i32 14 ret i32 %B 15} 16 17define signext i8 @test1(i32 %A) { 18; CHECK-LABEL: test1: 19; CHECK: @ %bb.0: 20; CHECK-NEXT: sbfx r0, r0, #8, #8 21; CHECK-NEXT: bx lr 22 %B = lshr i32 %A, 8 23 %C = shl i32 %A, 24 24 %D = or i32 %B, %C 25 %E = trunc i32 %D to i8 26 ret i8 %E 27} 28 29define signext i32 @test2(i32 %A, i32 %X) { 30; CHECK-DSP-LABEL: test2: 31; CHECK-DSP: @ %bb.0: 32; CHECK-DSP-NEXT: sxtab r0, r1, r0, ror #8 33; CHECK-DSP-NEXT: bx lr 34; 35; CHECK-NO-DSP-LABEL: test2: 36; CHECK-NO-DSP: @ %bb.0: 37; CHECK-NO-DSP-NEXT: sbfx r0, r0, #8, #8 38; CHECK-NO-DSP-NEXT: add r0, r1 39; CHECK-NO-DSP-NEXT: bx lr 40 %B = lshr i32 %A, 8 41 %C = shl i32 %A, 24 42 %D = or i32 %B, %C 43 %E = trunc i32 %D to i8 44 %F = sext i8 %E to i32 45 %G = add i32 %F, %X 46 ret i32 %G 47} 48 49define i32 @test3(i32 %A, i32 %X) { 50; CHECK-DSP-LABEL: test3: 51; CHECK-DSP: @ %bb.0: 52; CHECK-DSP-NEXT: sxtah r0, r0, r1, ror #8 53; CHECK-DSP-NEXT: bx lr 54; 55; CHECK-NO-DSP-LABEL: test3: 56; CHECK-NO-DSP: @ %bb.0: 57; CHECK-NO-DSP-NEXT: sbfx r1, r1, #8, #16 58; CHECK-NO-DSP-NEXT: add r0, r1 59; CHECK-NO-DSP-NEXT: bx lr 60 %X.hi = lshr i32 %X, 8 61 %X.trunc = trunc i32 %X.hi to i16 62 %addend = sext i16 %X.trunc to i32 63 %sum = add i32 %A, %addend 64 ret i32 %sum 65} 66 67define signext i32 @test4(i32 %A, i32 %X) { 68; CHECK-DSP-LABEL: test4: 69; CHECK-DSP: @ %bb.0: 70; CHECK-DSP-NEXT: sxtab r0, r1, r0, ror #16 71; CHECK-DSP-NEXT: bx lr 72; 73; CHECK-NO-DSP-LABEL: test4: 74; CHECK-NO-DSP: @ %bb.0: 75; CHECK-NO-DSP-NEXT: sbfx r0, r0, #16, #8 76; CHECK-NO-DSP-NEXT: add r0, r1 77; CHECK-NO-DSP-NEXT: bx lr 78 %B = lshr i32 %A, 16 79 %C = shl i32 %A, 16 80 %D = or i32 %B, %C 81 %E = trunc i32 %D to i8 82 %F = sext i8 %E to i32 83 %G = add i32 %F, %X 84 ret i32 %G 85} 86 87define signext i32 @test5(i32 %A, i32 %X) { 88; CHECK-DSP-LABEL: test5: 89; CHECK-DSP: @ %bb.0: 90; CHECK-DSP-NEXT: sxtah r0, r1, r0, ror #24 91; CHECK-DSP-NEXT: bx lr 92; 93; CHECK-NO-DSP-LABEL: test5: 94; CHECK-NO-DSP: @ %bb.0: 95; CHECK-NO-DSP-NEXT: sxth.w r0, r0, ror #24 96; CHECK-NO-DSP-NEXT: add r0, r1 97; CHECK-NO-DSP-NEXT: bx lr 98 %B = lshr i32 %A, 24 99 %C = shl i32 %A, 8 100 %D = or i32 %B, %C 101 %E = trunc i32 %D to i16 102 %F = sext i16 %E to i32 103 %G = add i32 %F, %X 104 ret i32 %G 105} 106